Citi Bank Launching The Credit Card In Asia Pacific Essay

Citi Bank Launching The Credit Card In Asia Pacific - Essay Example The feasibility of launching the product in Singapore would become clear in the light of the following analysis: Income and Standard of Living: Singapore is a country of rich and affluent people with an average per capita income of $8,817 that is continuously growing at a higher rate than other countries in the region and a standard of living much better as compared to most of its neighbouring countries. Most of the population can conveniently afford a credit card therefore this country offers great opportunity to the Citi corp. in launching its product for the first time in the whole region. Therefore, the land of Singapore offers more opportunities than risk for the Citi Bank credit card launch. Although risks are there, but the country having 100% urban population, higher per capita income and much better standard of living offer less country risks to the launch of a product like credit card. Although the country profile of Singapore offers has great attractiveness for the launch of Citi Bank credit card, yet the market ... Although the country profile of Singapore offers has great attractiveness for the launch of Citi Bank credit card, yet the market profile suggests a great number of risks associated with it. The credit card market has been already captured by major international players such as American Express Bank, Hong Kong Bank, Chase, Standard Chartered and local banks such as UOB, DBS, OUB, and OCBC, which make it very difficult for a bank to successfully enter the market and remain profitably in business for long. In order to enter the Singapore market and successfully launch the product, Citi Bank could either purchase an existing already established business, or launch a rigorous marketing campaign to attract a great number of customers or can even both the options simultaneously as suggested by the case given. However it is recommendable for the Citi Bank to go for the development of its product's own market. The bank should adopt a number of possible marketing strategies that could help it achieve the objective of customer awareness and customer acceptance. Initially, the customers should be made acquainted to the product and then the product must be positioned in a way to win the customer acceptance. Competitive Advantage Singapore is a market where people enjoy a high standard of living and therefore, enjoy the products that are associated with image, status and recognition. Citi Bank can take advantage of this attitude by positioning the credit card and associate its image with high status, prestige, affluence and style. The bank should use its "international identity" and offer its product to the people with maximum international usage and recognition. This can be the most visible competitive advantage readily available to be

Interrelationships with Culture and Visual Entertainmen Essay Example for Free

Interrelationships with Culture and Visual Entertainmen Essay Culture and visual entertainment media have an interrelationship with each other such as film and television. As the years go by and more and more television shows and movies have been created they have in my opinion become of a reflection of our cultural times. Society is watching the films and television and seeing that they can relate to what they are watching which then they are able to take away a message. People can see visual instead of having to read to learn which can give them a different perspective that they may not have thought of on their own. As people view the visual entertainment they and see what is being influenced from the way people act, dress, talk, and so forth since it is what is shaping our culture. The Brady Bunch is an example of how families were starting to see that families can merge together and become one family, the outfits and hairstyles were being mimicked by people in everyday life. I remember watching this show thinking how â€Å"cool† is it to have two families merge together. This showed that the social influences of visual entertainment media can be positive. People can still watch visual media that is been out dated but still learn about American culture with such shows. Another example is â€Å"The Breakfast Club† this movie is a classic and still very relevant to how our American culture is shaped. In this movie they look at individuals and show that even though we are from all walks of life such as a jock, nerd, snob, shy, and criminal that we all have similarities in the end if we stop and take a moment to see. I Love Lucy† was a huge influence on visual entertainment people wanted to have the grace, the silliness, and could also see that they lived modestly which made it relate to society. Visual media can be negative as well a positive influence on social behavior. When we view visual entertainment I would say majority want to emulate the celebrities that they are viewing which can be negative or positive depending on that moment. People want to fit in society and with visual entertainment that can shape them in to something different. I remember during the eighty’s all of the shows and movies I watch were all the underdog wins in the end and I felt that this is what I want I want to be the underdog the stand along and befriends with everyone. Guess what I was that person I still am that person as well as I take up for the underdog and befriend everyone as well as treat everyone with respect no matter what. I can thank â€Å"Sixteen Candles, Full House, The Breakfast Club, The Outsiders, and I Love Lucy† were all visual entertainment that made me who I am as well as a lot of others.

Payment Systems For E Commerce

Payment Systems For E Commerce The emergence of e-commerce has effectively created many new financial needs which in many cases cannot be fulfilled by traditional payment systems. By considering all of these aspects many organizations are exploring various types of electronic payment systems and digital currency and also various issues regarding these payment systems. Broadly electronic payment system is classified in to mainly into four categories: Online Credit card Payment system, Online Electronic Cash system, Electronic Cheque System and Smart Cards based Electronic payment system. Every system has its advantages and disadvantages for the customers and merchants. These systems have number of requirements: e.g. acceptability, convenience, security, cost, anonymity, control, and traceability. Hence, instead of focusing on the technological specifications of various e payment systems, the researchers have distinguished e payment system based on what is transmitting over the network; analyze the difference of eac h electronic payment systems based on their requirements, characteristics and assess the applicability of every system. I. INTRODUCTION Payment is the integral process in the mercantile process, electronic payment system is the integral part of the electronic commerce. Due to the emergence of electronic commerce has created new financial needs through which need for new payment systems has created while traditional payment system cannot be able to fulfill its needs. For example new payment systems are of the forms such as auctions between individual ¿Ã‚ ½s online results in searching for new payment systems that means peer to peer payment methods that allows individuals to make payments through their e-mails. By recognizing these needs all interested parties (i.e: government, business communities and financial service providers) are invading various types of electronic payment systems and issues regarding those payment systems and electronic currency. Some of the proposed systems are electronic type of the traditional payment system such as credit cards, cheques, while, others are based on the digital currency tech nology and have the potential for definitive impact on today ¿Ã‚ ½s financial and monetary system. While popular developers of electronic payment system predict fundamental changes in the financial sector because of the innovations in electronic payment system (Kalakota Ravi, 1996). Therefore in particular electronic commerce have many methods of payment systems, these methods of payment systems are developed to support the electronic commerce. A failure to take place these developments into the proper context is likely to result in undue focus on the various experimental initiatives to develop electronic forms of payment without a proper reflection on the broader implications for the existing payment system. The table below shows a steady increase in the annual growth of total U.S. e-commerce sales for the 2000-2009 periods. A. CONCEPT AND SIZE OF ELECTRONIC PAYMENT The payment systems that uses electronic distribution networks constitute a frequent system in the banking and business sector since 1960 ¿Ã‚ ½s, especially for the transfer of large amounts of money. In the four decades that have passed since their appearance, necessary technological developments have taken place, which on the one hand have expanded the possible technologies of electronic payment systems besides they have also created new social and business practice, which make the use of these systems necessary. These changes, naturally, have affected the definition of electronic payments, which is emerging depending on the needs of each period. In most general form, the word electronic payment comprised of any payment (transactions) to businesses, bank or public services from citizens or businesses, which are made through a telecommunications or electronic networks by using modern technology. It is obvious that based on this definition, the electronic payments that will be the objects of present result, is the payment that is executed by the payer by himself, whether the latter is a consumer or a business, without the intervention of the another natural person. Furthermore, these payments are made from distance, without the presence of the payer physically and naturally it does not include cash. By providing such definition for the electronic payment system, this make researches to include the information concerning the accounts of the parties involved in the transaction, and also technological means of transaction execution such as distribution channel etc. Size of Electronic Payments: Electronic payments can be made in different forms, based on these forms electronic commerce payments systems are categorized as Business-to-Business (B2B), Business-to-Consumer (B2C), Consumer-to-Business (C2B) and Consumer-to-Consumer (C2C). Each of which has special characteristics that depend on the value of order. Danial, (2002) classified electronic payment systems as follows:  ¿Ã‚ ½ Micro Payment (less than $ 10) that is mainly conducted in C2C and B2C e-commerce.  ¿Ã‚ ½ Consumer Payment that has a value between $ 10 and $ 500. It is conducted mainly in B2C transactions.  ¿Ã‚ ½ Business Payment that has the value more than $ 500. It is conducted mainly in B2B e-commerce. B. CONVENTIONAL VS. ELECTRONIC PAYMENT SYSTEM To dig the depth of the electronic payment process, it is better to first understand the processing of traditional payment system. A traditional process of payment and settlement involves a buyer-to-seller transfer of cash or payment information (i.e., cheque and credit cards). The general settlement of payment process takes place in the financial processing network. A cash payment requires a buyer ¿Ã‚ ½s withdrawals form his/her bank account, a transfer of cash to the seller, and the seller ¿Ã‚ ½s deposit of payment to his/her account. Non-cash payment systems are settled by adjusting i.e. crediting and debiting the appropriate accounts between banks based on payment information conveyed via cheque or credit cards. Figure 1: Conventional/Traditional Payment System Figure is simplified diagram for both cash and non-cash transactions. As cash Transferred from the buyer ¿Ã‚ ½s bank to seller ¿Ã‚ ½s bank through face-to-face exchange in the market. If a buyer uses a non-cash form of payment, payment information instead of cash flows from the buyer to the seller, and payments are settled between affected banks, who notationally adjust accounts based on payment information. C. PROCESS OF ELECTRONIC PAYMENT SYSTEM Electronic payment system have been operating since 1960s and also expanding very rapidly as well as growth and complexity. After the development of traditional payment system new features such as Electronic Funds Transfer based payments methods came in to existence. It was the first electronic based payment system, which does not depend on intermediary of central processing. An electronic fund transfer is a financial application of EDI (Electronic Data Interchange), which transfers credit card numbers or electronic cheques via secured private transfer lines between banks and major corporations. To use EFT to clear payments and settle accounts, online payment services needs all the capabilities to process the order, accounts and receipts. But a landmark came in to direction with the development of digital currency. Use of electronic money and digital currency looks alike the paper money as a means of payment. Digital based currency system is having same advantages as of paper based c urrency system those are namely anonymity and convenience. As in other electronic payments systems (i.e. EFT based and intermediary based) here is also concern about the security in the electronic payment systems during the transactions and storage is also a main concern, although from the different perspective, for digital currency systems double spending, counterfeiting, and storage become critical issues whereas eavesdropping and the issue of liability (when charges are made without authorizations) is important for the notational funds transfer. Figure 2 shows digital currency based payment system. In this figure, it is shown that intermediary acts as an electronic bank, which converts outside money (e.g. Rupees or US $), into inside money (e.g. tokens or e-cash), which is circulated within online markets. However, as a private monetary system, digital currency has wide ranging impact on money and monetary system with implications extending far beyond more transactional efficiency. II. TYPES OF ELECTRONIC PAYMENT SYSTEMS With the rapid growth in the electronic commerce need for the payment systems are increased as that of e commerce by which dozens of payments systems are came in to existence and also they are already in practice. Grouping of these payments systems are made based upon the information being transferred online. Murthy (2002) explained six types of electronic payment systems: (1) PC-Banking (2) Credit Cards (3) Electronic Cheques (i-cheques) (4) Micro payment (5) Smart Cards and (6) E-Cash. Kalakota and Whinston (1996) identified three types of electronic payment systems: (1) Digital Token based electronic payment systems, (2) Smart Card based electronic payment system and (3) Credit based electronic payment systems. Dennis (2001) classified electronic payment system into two categories: (1) Electronic Cash and (2) Electronic Debit-Credit Card Systems. Thus, electronic payment system can be broadly divided into four general types (Anderson, 1998):  ¿Ã‚ ½ Online Credit Card Payment System  ¿Ã‚ ½ Electronic Cheque System  ¿Ã‚ ½ Electronic Cash System and  ¿Ã‚ ½ Smart Card based Electronic Payment System Online Credit Card Payment System: It seeks to extend the functionality of existing credit cards for use as online shopping payment tools. This payment system has been widely accepted by consumers and merchants throughout the world, and by far the most popular methods of payments especially in the retail markets (Laudon and Traver, 2002). These forms of payment systems are having many advantages, which were never available through the traditional payments methods. Some of the advantages of the online credit card payment systems are: privacy, integrity, compatibility, good transaction efficiency, acceptability, convenience, mobility, low financial risk and anonymity. Added to all these, to avoid the complexity associated with the digital cash or electronic-cheques, consumers and vendors are also looking at credit card payments on the internet as one of possible time-tested alternative. But, this payment system has raised several problems before the consumers and merchants. Online cred it card payment systems are also having many disadvantages lack of authentication, repudiation of charges and credit card frauds. It also seeks to address consumer fears about using credit card such as having to reveal credit information at multiple sites and repeatedly having to communicate sensitive information over the Internet. Basic process of Online credit card payment system is very simple as that of traditional payment systems. If consumers want to purchase a product or service, they simply send their credit card details to the service provider involved and the credit card organization will handle this payment like any other. This can be understood very easily with the format (Figure 3) of Credit Card Payment Form. Electronic Cheque Payment System: Electronic cheque fulfills the needs of many business organizations, which are previously exchanging paper based cheque based on the vendors, consumers and government. Working process of e-cheque is as same as that of the traditional cheque payment system. An account holder will issue the electronic cheque document which contains the information such as name of the account holder payee name, name of the financial institution, payer ¿Ã‚ ½s account number and the amount of payment on the cheque. Most of the information is in un coded form. Like a paper cheques e-cheques also bear the digital equivalent of signature: a computed number that authenticates the cheque from the owner of the account. Digital checking payment system seeks to extend the functionality of existing checking accounts for use as online shopping payment tools. Electronic cheque system has many advantages: (1) they do not require consumers to reveal account information to other indi viduals when setting an auction (2) they do not require consumers to continually send sensitive financial information over the web (3) they are less expensive than credit cards and (4) they are much faster than paper based traditional cheque. But, this system of payment also has several disadvantages. The disadvantage of electronic cheque system includes their relatively high fixed costs, their limited use only in virtual world and the fact that they can protect the users? anonymity. Therefore, it is not very suitable for the retail transactions by consumers, although useful for the government and B2B operations because the latter transactions do not require anonymity, and the amount of transactions is generally large enough to cover fixed processing cost. The process of electronic checking system can be described using (figure 4) the following steps. Step 1: a purchaser fills a purchase order form, attaches a payment advice (electronic cheque), signs it with his private key (using his signature hardware), attaches his public key certificate, encrypts it using his private key and sends it to the vendor. Step 2: the vendor decrypts the information using his private key, checks the purchaser ¿Ã‚ ½s certificates, signature and cheque, attaches his deposit slip, and endorses the deposit attaching his public key certificates. This is encrypted and sent to his bank. Step 3: the vendor ¿Ã‚ ½s bank checks the signatures and certificates and sends the cheque for clearance. The banks and clearing houses normally have a private secure data network. Step 4: when the cheque is cleared, the amount is credited to the vendor ¿Ã‚ ½s account and a credit advice is sent to him. Step 5: the purchaser gets a consolidated debit advice periodically. E-cheque provide a security rich Internet payment option for businesses and offer an easy entry into electronic commerce without a significant investment in new technologies or legal systems. Electronic Cash Payment System: Electronic payment system is new technology in the online payment systems which improve the features such as security and privacy because it combines computerized convenience. Its versatility opens up a host of new markets and applications. E-cash is an electronic or digital form of value storage and value exchange that have limited convertibility into other forms of value and require intermediaries to convert. E-cash presents some characteristics like storability, monetary value, interoperability, irretrievability, and security. // By using all these characteristics it makes electronic cash more attractive payment system on the internet (Online). Added to these, this payment system offers numerous advantages like privacy, good acceptability, authority, convenience, low transactions cost and good anonymity. But, this system of payment also has many disadvantages such as poor transaction efficiency, poor mobility, and high financial risk, as people are solely responsible for the lost or stolen. Gary and Perry (2002), just like real world currency counterpart, electronic cash is susceptible to forgery. It is possible, though increasingly difficult, to create and spend forged e-cash. E-Cash Structure: e-cash structure could be identified as a string of bits that represents certain values such as reference number and digital signature, which could be used for the security purpose to prevent forgery and criminal use (Wright, 2002). But, the structure proposed by Wright (2002) needs some extension to make e-cash more secure. Therefore, the present model (Figure 3.5) adds a digital watermark to e-cash structure to protect it from the illegal copy and forgery activities further, the model modified the structure of the reference number to support tractability as shown in the figure 5. The proposed e-cash structure is comparatively better than suggested by Wright (2002), because security issue is given importance of top most priority in the present model. But, still there are certain concerns to be addressed for an electronic cash system. For example, who has the right to issue electronic cash? Can every bank issue its own money? If so how do you prevent fraud? And who will monitor the banking operations to protect consumers? Many of these concepts relate to the legal and banking regulatory aspects. However all these issues are beyond the scope of the study and therefore, cannot be included here. But, these issues must be addressed before establishing a complete e-cash based payment system. Smart Cards based Electronic Payment System: Smart cards are receiving renewed attention as a mode of online payment. They are essentially credit card sized plastic cards with the memory chips and in some cases, with microprocessors embedded in them so as to serve as storage devices for much greater information than credit cards with inbuilt transaction processing capability. This card also contains some kinds of an encrypted key that is compared to a secret key contained on the user ¿Ã‚ ½s processor. Some smart cards have provision to allow users to enter a personal identification number (PIN) code. Smart cards have been in use for well over the two decades now and have been widespread mostly in Europe and Asian Countries. Owing to their considerable flexibility, they have been used for a wide range of functions like highway toll payment, as prepaid telephone cards and as stored value debit cards. However, with the recent emergence of e-commerce, these devices are increasingly being viewed as a particularly appropriate method to execute online payment system with considerably greater level of security than credit cards. Compared with traditional electronic cash system, smart cards based electronic payment systems do not need to maintain a large real time database. They also have advantages, such as anonymity, transfer payment between individual parties , and low transactional handling cost of files. Smart cards are also better protected from misuse than, say conventional credit cards, because the smart card information is encrypted. Currently, the two smart cards based electronic payment system- Mondex and Visa Cash are incompatible in the smart cards and card reader specification. Not knowing which smart card system will become market leader; banks around the world are unwilling to adopt either system, let alone other smart card system. Therefore, establishing a standard smart card system, or making different system interoperable with one another is critical success factors for smart card based payment system. Kalakota and Whinston (1996), classified smart cards based electronic payment system as (1) relationship based smart cards and electronic purses. Electronic purses, which may replace money, are also known as debit card. Further Diwan and Singh (2000) and Sharma and Diwan (2000), classified smart cards into four categories. These are: (1) memory cards: this card can be used to store password or pin number. Many telephone cards use these memory cards (2) shared key cards: it can store a private key such as those used in the public key cryptosystems. In this way, the user can plug in the card to a workstation and workstation can read the private key for encryption or decryption (3) signature carrying card: this card contains a set of pre generated random numbers. These numbers can be used to generate electronic cash (4) signature carrying cards: these cards carry a co-processor that can be used to generate large random numbers. These random numbers can then be used for the assignment as serial numbers for the electronic cash. III. CONCLUSION Technology created lives easier for human beings. It has decreases the work up to many extends such as distance space and even time. One of the technological innovation in the banking and financial sectors is the electronic payments. // By using electronic payments we can perform financial operations electronically, thus avoiding long lines and other hassles. Electronic Payments provides greater freedom to individuals in paying their licenses, taxes, fees, fines and purchases at unconventional locations and at whichever time of the day, 365 days of the year. On the basis of present study, first remark is that despite the existence of variety of e-commerce payment systems, credit cards are the most dominant payment system. This is consequences of advantageous characteristics, most importantly the long established networks and very wide user ¿Ã‚ ½s base. Second, alternative e-commerce payment systems are some countries are debit cards. In fact, like many other studies, present study also reveals that the smart card based e-commerce payment system is best and it is expected that in the future smart cards will eventually replace the other electronic payment systems. Third, given the limited users bases, e-cash is not a feasible payment option. Thus, there are number of factors which affect the usage of e-commerce payment systems. Among all these user base is most important. Added to this, success of e-commerce payment systems also depends on consumer preferences, ease of use, cost, industry agreement, authorization, security, authentication, non-refutability, accessibility and reliability and anonymity and public policy. IV. REFERENCES 1. Abrazhevich, D. (2002) ,Diary on Internet Payment Systems ¿Ã‚ ½, Proceedings of the British Conference on Human Computer Interaction, London, England. 2. Anderson, M.M. (1998),  ¿Ã‚ ½Electronic Cheque Architecture, Version 1.0.2 ¿Ã‚ ½, Financial Services Technology Consortium, September 3. Baddeley, M. (2004)  ¿Ã‚ ½Using E-Cash in the New Economy: An Electronic Analysis of Micropayment Systems ¿Ã‚ ½, Journal of Electronic Commerce Research, Vol. 5, No. 4, pp 239-253. 4. Bhatia, Varinder (2000), E-Commerce (Includes E-Business), New Delhi: Khanna Book Publishing Co. 5. Boly, J. P. et al., (1994),  ¿Ã‚ ½ The ESPRIT Project CAF ¿Ã‚ ½-High Security Digital Payment System ¿Ã‚ ½, ESORICS 94, Third European Symposium on Research in Computer Security, Brighton, LNCS 875, Spring- Verlage, Berlin, pp 217-230. accessed on http://www.zurich.ibm.ch/technology/Security/Sirene/Publ/ BBCM1_94cafeEsorics.ps.gz. 6. Cavarretta, F. and de Silva, J. (1995),  ¿Ã‚ ½Market Overview of the Payments Mechanisms for the Internet Commerce ¿Ã‚ ½, accessed on http://www.mba96.hbs.edu/fcavarretta/money.html. 7. Chakrabarti, Rajesh and Kardile, Vikas (2002), E-Commerce: The Asian Manager ¿Ã‚ ½s Handbook, New Delhi: Tata McGraw Hill. 8. Charkrabarthi, Rajesh et al (2002), The Asian Manager ¿Ã‚ ½s Handbook of E-Commerce, New Delhi: Tata McGraw Hill.) 9. Chaum, D. (1992),  ¿Ã‚ ½Achieving Electronic Privacy ¿Ã‚ ½, Scientific American, August,pp 96-101 accessed on http://www.digicash.support.nl/publish/sciam.html. 10. Danial, Amor (2002), E-Business (R) evolution, New York: Prentice Hall. 11. Dennis, Abrazhevich (2001),  ¿Ã‚ ½Classifications and Characteristics of Electronic Payment Systems ¿Ã‚ ½, Lecture Notes in Computer Science, Vol. 21, No. 5, pp. 81-90.

Ralphs Leadership in William Golding’s Lord of the Flies Essay

Ralph's Leadership in William Golding’s Lord of the Flies Ralph, the elected leader of the group of British boys in William Golding’s Lord of the Flies, strives to take the civilized society to which he is accustomed and apply it to society on the island on which he and the other boys are stranded. As leader, this task seems simple – tell the other boys what they each need to do and expect them to do it. Ralph fails to realize the difference between the rest of the boys and himself. The world is in the middle of a massive war, a war in which the threat of the atomic bomb looms prominently. In fear of losing all its future fighting force, Britain sends a group of its schoolboys on an airplane to safety. Before reaching its destination, though, an enemy fighter plane shoots down the boys’ plane. The plane crashes into a forest on a remote island and, as a result, the pilots die. This group of schoolboys jumps from a society in which adults direct them to act properly to one in which there is no authoritative figure to give them orders. Back in Britain, adults train the boys to obey them and follow their lead. They act appropriately because of the threat of punishment for disobedience. Even later in the novel, once things begin to fall apart, Golding writes, â€Å"Here, invisible yet strong, was the taboo of the old life. Round the squatting child was the protection of parents and school and policemen and the law† (62). As the story progresses, though the boys go so far as to participate in savage acts such as killing each other, in the end, they realize that they conducted themselves immorally. Stranded on the island with a bunch of boys and no adults, Ralph quickly takes charge and demands the election of a leader of the bo... ...ings a type of closure to the ordeal, and it also shows a realization he had about society, about mankind in general. He has witnessed with his own eyes the evil that comes about as a result of the lack of civilization and the inborn nature to do evil. Golding describes Ralph’s profound crying simply: â€Å"Ralph wept for the end of innocence, the darkness of man’s heart, and the fall through the air of the true, wise friend called Piggy† (202). While nearly all the boys on the island ignore those standards British society has taught them, Ralph does not, and, as leader, tries to apply them to society on the island. Even when everyone else reverts to his inborn evil nature, Ralph sticks with that which is good, that which he learned from British society – civility. Ralph is different than the other boys, and because of that difference, it is only fitting that he cry.

Criminal Acts and Choice Theories

Criminal Acts and Choice Theories CJA/204 December 13, 2011 Bob Bennett The choice theory has a substantial part to perform when contemplating the argumentation proceeding to criminal vivacity. The choice theory has its intrinsic significance while composing a plan of action for managing or decreasing crime. It is essential to recognize the theory and in what way or manner it influences the potential of an individual engaging in lawlessness and in what manner would an effort to manage crime appear supporting the choice theory. The choice theory has been brought to light from the compositions of antecedent theorists, Jeremy Bentham, and Cesare Beccaria. The affects of the choice theory determines how mankind discourages criminal activity (Schmallager, 2009). Within criminology the choice theory is also distinguished as the classical theory. The principle idea of the classical theory is that individuals cull behavior with the addition of criminal conduct. Individual powers of selection can be managed by multiple determinants such as the apprehension of castigation or the benefits achieved by committing a crime or illegal activities, which indicates that the more harsh, definite, and prompt the punishment, the better the chances to manage criminal conduct. The choice theory mentions that castigation should maintain four predominant ambitions. The first ambition is to use punishment to hamper criminal activity from occurring. A secondary principle maintains that when a crime cannot be hindered, the punishment should impel the offender to perpetrate a minor crime instead. The third ambition is to make certain that the offender applies no more violence than needed during a crime. The final objective is to counter crime as economically feasible. Rational choice is the judgment to perform a distinct kind of lawlessness or illegal activity established on the careful consideration of accessible information, combined with the element of personal judgment. The ational choice theory contains an outlook of crime that continues to be both offense and offender explicit. Offense-explicit lawlessness relates to crimes, where perpetrators will respond to selective attributes of specific offenses. Offender-explicit offenses relate to the reality that perpetrators are not easily provoked individuals who obligate him or her selves to antisocial behavior. Rather, he or she deliberate about whether they retain the prerequisi tes required for performing a lawless act that include their needs, ingenuity, talents, and apprehension level before determining to act out a crime. Choice theorists believe that criminal conduct is a personality characteristic and crime is a happening or event. Offenders recognize the freedom of mobility and privation of social restrictions. In contrast to other individuals, offender-explicit individuals have diminished self-control and seen unaffected by the intimidation of social controls. He or she is usually dealing with stress or is commonly confronted with severe personal complications or circumstances that drive them to adopt perilous behavior (Schmallager, 2009). Choice theorists have also examined the choice to perform a lawless act, regardless of its element, is contrived by the choice of location. The determination will rely upon the features of the mark and the methods available to execute the plan. It has been determined that offenders choose the location by the accessibility and ease of committing a crime with thoughts about the possibility of getting caught. Offenders pick their targets by pondering the character of the crime. A perfect example of this is how offenders will choose higher class households for burglaries or robberies, whereas he or she will select lower class households for the target of violent crimes such as in drug robberies from drug houses. Criminals learn the techniques of crimes to aid them in non-detection (Schmallager, 2009). Routine activities can be defined by the choice theory when discussing crime. Crimes rates correlate to the number of inspired criminals such as male teenagers, drug consumers, and unemployed individuals who partake in criminal activity. Most offenders commit crimes based on his or her narrow education, background, and lack of opportunities because of their education. If offenders were given the opportunities to improve themselves, he or she would not commit crimes. The rational choice theory includes the organization of crime and the molding of criminality (Schmallager, 2009). Society uses a couple of common models to decide which acts are determined to be criminal acts. The two models within the criminal justice system are consensus model and conflict model. Consensus model is defined as majority of individuals in a society who share the same values and beliefs. Criminal acts conflict with consensus values and beliefs, and here the term ‘conflict model’ comes into play. The consensus model explains that individuals within a society will agree on which activities should be considered against the law and will publish them as crimes. The consensus model assumes that a diverse group of individuals can have similar morals and beliefs. The consensus model presumes that when individuals stand together to form a society; the members will come to a fundamental agreement with the observance of shared norms, values, and beliefs. Individuals whose actions deviate from the standard norms and recognized values, and beliefs are considered to be a threat to the well-being of society, and must be punished. Societies pass laws to control and impede deviant behavior, which in return establishes boundaries for appropriate behavior within the society (Schmallager, 2009). The conflict model establishes those who reject consensus on the foundation that morals, norms, ideas, values, or behaviors are not absolute, meaning, multiple parts of society hold different ideas about value and norm systems. The conflict model carries diverse segments, which are separated into age, social class, race, and income. Those who engage in the idea of the conflict model are in a constantly struggling with one another for control of society. Those who successfully grasp control make the laws with his or her value system, and determine what is criminal and what is not (Schmallager, 2009). Resources; Schmallager, F. (2009). Criminal Justice Today, 10th ed. Upper Saddle River, N. J. Pearson/Prentice Hall

Free Essays on Achilles

Although the very first line of the Iliad state that it is Achilles’ anger that costs the Achaians thousands of lives, it is actually the Trojans who suffer the price of his anger. The Achaians suffered because of his pride. When Agamemnon says that he is the most important warrior (1. 185-187), Achilles becomes angry, but his pride had already prompted him to threaten retreat rather than suffer the insult of having Briseis taken. â€Å"And now my prize you threaten in person to strip from me†¦I am returning to Phthia, since it is much better to go home†¦I am minded no longer to stay here dishonored†¦Ã¢â‚¬  (1. 161-171) When Agamemnon’s herald’s come to take Briseis, he vows not to fight until the battle reaches his own ships. (1. 335-342). As the Achaians’ losses mount, Agamemnon sends Odysseus to persuade Achilles to help. Once again, it is Achilles pride that stops him from accepting Agamemnon’s offering and joining the battle. Although he states other reasons - that he was truly in love with Briseis (9. 341-343) and that he’d rather live a long and obscure life (9. 411-420) - it is his still wounded pride that motivates his decision. His pride and honor must be restored, and only an apology from Agamemnon will do: â€Å"All the other prizes of hounour he gave the great men and the princes are held fast by them, but from me alone of all the Achaians he has taken and keeps the bride of my heart†¦Ã¢â‚¬  (9. 334-336) â€Å"†¦not if he gave me gifts as many as the sand or dust is, not even so would Agamemnon have his way with my spirit until he had made good to me all this heartrending insolence.† (9. 385-387) This need to have his wounded pride healed is made clear when he sees the injured Machaon driven past his ship. â€Å"†¦now I think the Achaians will come to my knee and stay there in supplication, for a need past endurance has come to them† (11. 608-609). Achilles makes it clear that it is not his fear o... Free Essays on Achilles Free Essays on Achilles Although the very first line of the Iliad state that it is Achilles’ anger that costs the Achaians thousands of lives, it is actually the Trojans who suffer the price of his anger. The Achaians suffered because of his pride. When Agamemnon says that he is the most important warrior (1. 185-187), Achilles becomes angry, but his pride had already prompted him to threaten retreat rather than suffer the insult of having Briseis taken. â€Å"And now my prize you threaten in person to strip from me†¦I am returning to Phthia, since it is much better to go home†¦I am minded no longer to stay here dishonored†¦Ã¢â‚¬  (1. 161-171) When Agamemnon’s herald’s come to take Briseis, he vows not to fight until the battle reaches his own ships. (1. 335-342). As the Achaians’ losses mount, Agamemnon sends Odysseus to persuade Achilles to help. Once again, it is Achilles pride that stops him from accepting Agamemnon’s offering and joining the battle. Although he states other reasons - that he was truly in love with Briseis (9. 341-343) and that he’d rather live a long and obscure life (9. 411-420) - it is his still wounded pride that motivates his decision. His pride and honor must be restored, and only an apology from Agamemnon will do: â€Å"All the other prizes of hounour he gave the great men and the princes are held fast by them, but from me alone of all the Achaians he has taken and keeps the bride of my heart†¦Ã¢â‚¬  (9. 334-336) â€Å"†¦not if he gave me gifts as many as the sand or dust is, not even so would Agamemnon have his way with my spirit until he had made good to me all this heartrending insolence.† (9. 385-387) This need to have his wounded pride healed is made clear when he sees the injured Machaon driven past his ship. â€Å"†¦now I think the Achaians will come to my knee and stay there in supplication, for a need past endurance has come to them† (11. 608-609). Achilles makes it clear that it is not his fear o...

A Struggle for Dominance essays

A Struggle for Dominance essays In Mary Wollstonecraft Shelleys novel, Frankenstein, the protagonist, Victor Frankenstein, apparently has a struggle with his creation, over dominance. The creature eventually gains influence as he is enlightened by learning his surroundings. Victors creature learns to believe that he is Victors master, and Victor should do as he tells him. The struggle over dominance leads to a tragic end, as Victor loses his family, and eventually loses his own life as well. Victor Frankenstein decided to create something unique, being curious of nature ever since his encounter with lightning as a young boy. Upon creating something of his own, he became the modern Prometheus, who created something against the will of nature or God. He is much like Prometheus, who created beings against the will of his God, Zeus, and was punished. Victors monster becomes a constant interference is his life and a constant threat to the people he loves. Due to the lack of love Victor gave the creature, the monster decides to punish Victor, as Victor tries to forget the horror he has released unto the world. It could be said that now the creature dominates or is taking control over Victor, instead of Victor controlling his creation. Before Victor began the creation, he was overwhelmed with the thought of creating a being unlike any being that existed. Victor was cheerful, having a curiosity that would perhaps lead him to discover unknown secrets of life. Through this, we c an see that the thought of being superior (by curiosity) dominated Victor into creating a unique being. In his decision to play God, he will suffer the consequences. The creature is in search for revenge, due to the lack of love he was given since birth, I, the miserable and the abandoned, am an abortion, to be spurned at, and kicked, and trampled on (165). The creature tries to reason with Victor, by demanding him to create a female for...

Using the Comma in Spanish

Using the Comma in Spanish Most of the time, the comma in Spanish is used much like the comma in English. However, there are some differences, particularly in numbers and in comments that are inserted within sentences. Using Commas to Separate Items in a Series Unlike in English, where the Oxford comma  is optionally  used before the final item in a series, a comma is not used before the final item of a series when it follows the conjunction e, o, ni, u or y. El libro explicaba de una forma concisa, sencilla y profunda la crisis financiera. The book explained the financial crisis in a concise, simple and profound way. (In English, a comma could optionally be added after simple.)Mezcle bien con las papas, los huevos y las remolachas. (Mix well with the potatoes, eggs, and beets.) ¿Quieres tres, dos o una? (Do you want three, two, or one?) If an item in a series has a comma within it, you should use a  semicolon. Using Commas for  Explanatory Phrases and Apposition The rule on explanatory phrases is much the same as it is in English. If a phrase is used to explain what something is like, it is set off by commas. If it is used to define which something is being referred to, it is not. For example, in the sentence El coche que est en el garaje es rojo (The car that is in the garage is red), commas are not needed because the explanatory phrase (que est en el garaje/that is in the garage) is telling the reader which car is being discussed. But punctuated differently, the sentence el coche, que est en el garaje, es rojo (the car, which is in the garage, is red) uses the phrase not to tell the reader which car is being discussed but to describe where it is. An overlapping concept is that of apposition, in which a phrase or word (usually a noun) is immediately followed by another phrase or word that in the context means the same thing,  is similarly punctuated much as in English. El hombre, quien tiene hambre, quiere verte. (The man, who is hungry, wants to see you. The phrase quien  tiene hambre is being used to describe the man, not to define which man is being talked about.)El hombre en el cuarto quiere verte. (The man in the room wants to see you. No comma is needed because en el cuarto is being used to say which man is being talked about.)Amo a mi hermano, Roberto. I love my brother, Roberto. (I have one brother, and he is named Roberto.)Amo a mi hermano Roberto. I love my brother Roberto. (I have more than one brother, and I love Roberto.)Conozco a Julio Iglesias, cantante famoso. (I know Julio Iglesias, the famous singer.)Conozco al cantante famoso  Julio Iglesias. (I know the famous singer Julio Iglesias. The speaker is assuming that the listener doesnt know who Iglesias is.) Using Commas to Set Off Quotes When quotation marks are used, the comma goes outside the quotation marks, unlike in American English. Los familiares no comprendieron la ley, aclarà ³ el abogado. (The family members did not understand the law, the lawyer clarified.)Muchos no saben distinguir las dos cosas, dijo lvarez. (Many do not know how to distinguish the two things, Alvarez said.) Using Commas With Exclamations Commas can be used to set off exclamations that are inserted within a sentence. In English, the equivalent would normally be accomplished with long dashes. El nuevo presidente,  ¡no lo creo!, es oriundo  de Nueva York. The new president - I cant believe it! - is a native of New York. Using Commas Before Some Conjunctions A comma should precede conjunctions that mean except.  These words are excepto, salvo and menos: Nada hay que temer, excepto el miedo. (There is nothing to fear except fear.)Recibà ­ felicitaciones de todos, salvo de mi jefe. (I was congratulated by everyone except for my boss.)Fueron aceptados por todas las autoridades, excepto el vice presidente.  (They were accepted by all the authorities, except the vice president.) Using Commas After Some Adverbs A comma should separate adverbs or adverbial phrases that affect the meaning of the entire sentence from the rest of the sentence.  Such words and phrases often come at the beginning of a sentence, although they can also be inserted. Por supuesto, no puedo comprenderlo. (Of course, I cant understand it.)Por lo contrario, la realidad argentina no difiere de la dominicana.  (To the contrary, the Argentine reality doesnt differ from the Dominican reality.)Naturalmente, gana mucho dinero. Naturally, he earns a lot of money. (Without the comma, the Spanish sentence would become the equivalent of He naturally earns a lot of money, so that naturalmente would describe just the word gana rather than the entire sentence.)Sin embargo, pienso que eres muy talentosa.  (Nevertheless, I think youre very talented.)El trfico de bebà ©s, desgraciadamente, es una realidad.  (The trafficking of babies, unfortunately, is a reality.) Using Commas in Compound Sentences It is not unusual to join two sentences into one, often with y in Spanish or and in English. A comma should also be used before the conjunction. Roma es el centro espiritual del catolicismo, y su centro ha sido declarado Patrimonio de la Humanidad por UNESCO.  (Rome is the spiritual center of Catholicism, and its center has been declared a UNESCO World Heritage Site.)Muchos lagos se forman por la obstruccià ³n de valles debido a avalanchas, y tambià ©n se puede formar un lago artificialmente por la construccià ³n de una presa.  (Many lakes are formed by the obstruction of valleys due to avalanches, and a lake also can be formed artificially by the construction of a dam.) If a compound sentence is very short, the comma can be omitted: Te amo y la amo. (I love you and I love her.) Using the Decimal Comma In Spain, South America and parts of Central America, the comma and period are used in long numbers in the opposite way that they are in American English. Thus 123,456,789.01 in English becomes  123.456.789,01  in most areas where Spanish is used. However, in Mexico, Puerto Rico and parts of Central America, the convention used in American English is followed. When Not to Use the Comma Perhaps one of the most common misuses of the comma in Spanish by English speakers is its use in salutations in  letters. In Spanish, the salutation should be followed by a  colon. Thus letters should begin, for example, with Querido Juan: rather than following  Juan  with a comma. Also, as a general rule, as in English, a comma should not be used to separate the subject of a sentence from the main verb unless necessary to separate words of apposition or intervening phrases. Correct: El aà ±o pasado era muy difà ­cil. (The past year was very difficult.)Incorrect: El aà ±o pasado, era muy difà ­cil. (The past year, was very difficult.)

Why do many organizations fail to prove that traning has been a Essay

Why do many organizations fail to prove that traning has been a worthwhile business investment how might they go about doing this - Essay Example Indeed, employees perform better when they are happy (Philips, Jack, Patricia 2012, p. 39). Staff training is an essential and necessary step for specific reasons related to a business organization. On job training gives employees the chance to describe the broad knowledge that they had acquired during their early education with the specific needs of the organization (Bersin 2008, p.24). When workers are sure of their performance as acceptable to the management and organization needs they tend to feel important and happy with the business since they get satisfied with the result. There is always a direct connection between having happy workers and improving profit in all business organizations. Any organization that allows its employees to shoot hoops during work hours always leave clients with a lot of suspicions ( Price 2011, p. 24). Making the work environment, a bit tension that is constant has brought productivity in some organizations. Most workers leave their jobs in search of other position citing lack of skills training and development as their principal reason (B ebenroth 2015, p. 48). These movements of employees have a considerable impact on organization functioning as new employees have to be sought for replacement thus throwing the little experience that had been gained by the earlier workers to waste (Combs Davis 2010 p.55). Those that remain will be forced to double or even triple their effort to cover the gap. Workers morale will be affected in the process. Training by the organization can quickly take away the feeling of dissatisfaction thus making workers stay longer in their positions thus reducing the cost of turnover that cause slipping of business turnover (Bersin 2008, p.33). Though the initial cost of training may be high and discouraging, the benefits that the company stands to gain are much higher. Training of employees helps the

PRICE, CONSUMER BUYING BEHAVIOR AND MARKETING ACTIVITIES Essay

PRICE, CONSUMER BUYING BEHAVIOR AND MARKETING ACTIVITIES - Essay Example Pricing behaviors used to advertise goods and services to consumers such as twenty thousand pounds for a Ferrari, are common in contemporary society, showing that they are advantageous for businesses (Baines et al. 2011). Further, price consultants have emerged to provide advice to business people on how to price their goods because of existence of a strong relationship among price, consumer buying behavior, and marketing strategies. It is significant for businesses to determine which pricing behaviors will harness more consumers. Buying behavior is an act where people make decisions whether to buy a certain product or not. Consumer buying behavior is the buying behavior of the final consumer product. Consumers tend to show distinct behaviors when buying products and services of their choice. It is significant to note that the type of goods they want to purchase affects their purchasing behaviors. Consumer buying behavior incorporates a long process in that the purchaser has to ident ify and study the product advantages and disadvantages before deciding whether to purchase it or not. Since the intention of marketing is to ensure satisfaction of the customer in return for profits, business managers need to understand the relationship among price, consumer behavior, and marketing activities. Marketers need to identify customers’ needs, preferences, tastes, desires, and expectations of consumers in purchasing their products (Doyle 2006, pp. 73–4). ... Some buyers have an intricate purchasing behavior that is linked with different products that they intend to purchase (Grewal & Mamorstein 1994, p. 462). An intricate purchasing behavior is seen when the product to be bought is expensive; therefore, the consumer will tend to be more cautious when purchasing such products. For instance, intricate buying behavior is evident when purchasing things such as cars or computers. When setting prices for such products, marketers should consider the consumer’s income since high prices will drive them away (Lichtnstein 1993, p. 239). Price is one of the most significant marketplace signals. The issue of price is very important in buying situations since it represents to customers the amount of capital they must pay for a certain product. In addition, price represents how much money a consumer is going to give to a product seller in order to acquire a product; therefore, if prices are high, they negatively affect the chances of the consume r buying a particular item (Bolton et al. 2003, p. 476). Consumer perception of the price level of a particular product has a negative influence on the buying behavior of the consumer and an indirect positive influence on buying intentions through product quality perceptions. This trend is attributed to the fact that consumers are heterogeneous in respect of their intentions and response to product prices (Lichtnstein et al. 1993, p. 241). In most cases, consumers utilize a product price to choose if they will purchase it or not. They utilize a product price to determine the efficiency and quality of that product since they tend to believe that high prices imply good quality. According to research by

For the U.S.Army Corps of Engineers. The paper itself is a position Essay

For the U.S.Army Corps of Engineers. The paper itself is a position paper that is recommending a policy or technology to be implemented or changed for your organization - Essay Example Focussing on the water resources management and safety, this policy is proposed to the Chief Information Officer of the organization. As changes are occurring to the environment, and by extension to water bodies, it is imperative to adopt the policies of the organization to ensure populations near water bodies are kept safe. Many water-related disasters have been witnessed in recent time where the number of casualties is astounding. The people living near water bodies, of in areas prone to water-related disasters need to be kept safe. Keeping them informed is one way of doing this, since it facilitates disaster preparedness. In the implementation of this policy, such populations will be trained on how to ensure their own safety in the event of disaster such as a tornado, hurricane, tsunami or related scenarios. Awareness camps can be taken to the communities involved, where people will have a one-on-one interaction with the trainers. This change will be managed by the civil works div ision of the USACE. Technology is very influential in reaching out to people, and can be used as a platform in this scenario (Overby, 2007). Take for instance, when doing community reach-out, the trainers can request for the people to give their emails. Using these email addresses, the Civil Works program can send out alerts, and informative articles concerning incumbent disasters. Continuous flow of information to the risk population will give the people awareness they need to keep them always prepared. The information would always avert casualties when these areas are hit by disasters. Intention of using emails as a media of educating the targeted population may be met with resistance though. Spam messages have become a notorious invasion of people’s privacy. This may cause reluctance in the people issuing out their email addresses. Assurance will, therefore, be needed. The trainers need to help the people understand that the emails

Impact of internet on travel agencies in UK Essay

Impact of internet on travel agencies in UK - Essay Example This essay "Impact of internet on travel agencies in UK" outlines the whole changes that the Internet brought in the travel industry. The travel agencies have a very hectic service to provide to its customers. Traveling to a new location is a very hectic and risky enterprise. The tourists have to take into account very small details in traveling which they might not consider when at home. These include travel and mode of travel, the costs and expenditures, the number of days that the tourists plan to stay, locations where they want to travel and the times set for that, food and accommodation, good maintenance services for clothing, dining, eating etc., and recreational spots etc. A travel agent therefore, not only has to help the tourist decide where he or she should go for the vacation but also has to take care of these essential and miniscule details. The more thorough the travel agent is in planning the whole trip for the client, the better ranked the company is. But all these arr angements cannot take place without the essential ingredient of money. The client’s choice of tourism spot is largely dictated by the amount of money he or she can spend on the trip. Again it is the travel agent who should have the ingenuity of choosing travel spot that is right for the client, is able to provide the necessary services required and lets the customer think that he or she is getting a great deal. So where does the internet help in all this? The internet simply stating, has become the tool that organizes and categorizes this vast information. into a form that is both comprehendible to the client and that is able to provide the necessary information to the reader, without encroaching too much (Deimezi and Buhalis, 2003, np)

American Women Coursework Example | Topics and Well Written Essays - 500 words

American Women - Coursework Example As John Briggs says â€Å"education played a large role in the women’s rights movement of the 20th century because it was seen as a key to success in gaining social, economic and political equality.† The education mainly comprised of subjects such as mathematics and home economics as it was understood that these subjects will help them in running their houses and educating their children. Also, subjects like child birth, hygiene and first aid were preferred by many women. Poor women were educated by well to do women who had the finance to attend schools (Briggs, n.d). Christie Anne Farhaan (1994) argued that U.S needed an educated citizenry and this in turn required the nurturing of the young by more educated mothers and so women’s education was very important (pg 16). The seven sisters was one of the first all women college which encouraged women to study liberal arts and had high academic standards which could be compared to that of men’s colleges. Since education was limited to the white women, colleges for the black women also sprang after the civil war.

Internal Revenue Codes Essay Example | Topics and Well Written Essays - 750 words

Internal Revenue Codes - Essay Example . Internal Revenue Bulletin (2004) stipulates guidance for capitalization of expenditures. There are a number of intangibles listed therein expenditures incurred for acquisition of which are required to be capitalized if they are held to be for more than 12 months period. Para 4 of section1.263 (a)-4 and 1.263(a)-5 are added in the bulletin to read as follows. (a) Overview. This section provides rules for applying section 263(a) to amounts paid to acquire or create intangibles. Except to the extent provided in paragraph (d)(8) of this section, the rules provided by this section do not apply to amounts paid to acquire or create tangible assets. Paragraph (b) of this section provides a general principle of capitalization. Paragraphs (c) and (d) of this section identify intangibles for which capitalization is specifically required under the general principle. Paragraph (e) of this section provides rules for determining the extent to which taxpayers must capitalize transaction costs. Paragraph (f) of this section provides a 12-month rule intended to simplify the application of the general principle to certain payments that create benefits of a brief duration. Additional rules and examples relating to these provisions are provided in paragraphs (g) through (n) of this section. The applicability date of the rules in this section is prov ided in paragraph (o) of this section. Paragraph (p) of this section provides rules applicable to changes in methods of accounting made to comply with this section. Terming a credit card agreement as a finacial interest as iten no 2 (i) ( c ) (2) at page 26, the bulletin states that aqusition expendtures for credit card should be capitalised. Analyzing the code 195, it has been found that it applies to capitalization of business start-up expeditures which can be deducted from the income over a certain period depending upon the election of the tax payer. Credit card acquisitions expenses do not come under the defintion of start-up expenditures as per section 195.( IRC ) Please refer to the Appendix A for defiintions. In addition to the above clearly defined calrifications, in FSA 200136010, the conlusion arrived at by the Service was that a bank must capitalize the expenditure involved in acquisition of credit card receivables. It includes also credit card accounts from other institutions. In this connection the bank had in its return "deducted the cost of acquiring and securitizing the credit card receivables" ( David J 2002), which the tax officer disallowed. On appeal by the bank against the deductions, it was pointed out that in the case of INDOCO Inc, 503 US 79 (1992), the IRS had already decided that credit card receivables were assets capable of giving future benefits along with interst.and that IRS further decided that it could not be amortized also under sec 195 which only provided for investigative expenses for starting a buisness and not for purchasing a partcular capital asset in reply to the contention of the bank that the expnses were of investigatory in nature and could therfore b e deducted. Under the circumstances, it is

Impact of internet on travel agencies in UK Essay

Impact of internet on travel agencies in UK - Essay Example This essay "Impact of internet on travel agencies in UK" outlines the whole changes that the Internet brought in the travel industry. The travel agencies have a very hectic service to provide to its customers. Traveling to a new location is a very hectic and risky enterprise. The tourists have to take into account very small details in traveling which they might not consider when at home. These include travel and mode of travel, the costs and expenditures, the number of days that the tourists plan to stay, locations where they want to travel and the times set for that, food and accommodation, good maintenance services for clothing, dining, eating etc., and recreational spots etc. A travel agent therefore, not only has to help the tourist decide where he or she should go for the vacation but also has to take care of these essential and miniscule details. The more thorough the travel agent is in planning the whole trip for the client, the better ranked the company is. But all these arr angements cannot take place without the essential ingredient of money. The client’s choice of tourism spot is largely dictated by the amount of money he or she can spend on the trip. Again it is the travel agent who should have the ingenuity of choosing travel spot that is right for the client, is able to provide the necessary services required and lets the customer think that he or she is getting a great deal. So where does the internet help in all this? The internet simply stating, has become the tool that organizes and categorizes this vast information. into a form that is both comprehendible to the client and that is able to provide the necessary information to the reader, without encroaching too much (Deimezi and Buhalis, 2003, np)

Internal Revenue Codes Essay Example | Topics and Well Written Essays - 750 words

Internal Revenue Codes - Essay Example . Internal Revenue Bulletin (2004) stipulates guidance for capitalization of expenditures. There are a number of intangibles listed therein expenditures incurred for acquisition of which are required to be capitalized if they are held to be for more than 12 months period. Para 4 of section1.263 (a)-4 and 1.263(a)-5 are added in the bulletin to read as follows. (a) Overview. This section provides rules for applying section 263(a) to amounts paid to acquire or create intangibles. Except to the extent provided in paragraph (d)(8) of this section, the rules provided by this section do not apply to amounts paid to acquire or create tangible assets. Paragraph (b) of this section provides a general principle of capitalization. Paragraphs (c) and (d) of this section identify intangibles for which capitalization is specifically required under the general principle. Paragraph (e) of this section provides rules for determining the extent to which taxpayers must capitalize transaction costs. Paragraph (f) of this section provides a 12-month rule intended to simplify the application of the general principle to certain payments that create benefits of a brief duration. Additional rules and examples relating to these provisions are provided in paragraphs (g) through (n) of this section. The applicability date of the rules in this section is prov ided in paragraph (o) of this section. Paragraph (p) of this section provides rules applicable to changes in methods of accounting made to comply with this section. Terming a credit card agreement as a finacial interest as iten no 2 (i) ( c ) (2) at page 26, the bulletin states that aqusition expendtures for credit card should be capitalised. Analyzing the code 195, it has been found that it applies to capitalization of business start-up expeditures which can be deducted from the income over a certain period depending upon the election of the tax payer. Credit card acquisitions expenses do not come under the defintion of start-up expenditures as per section 195.( IRC ) Please refer to the Appendix A for defiintions. In addition to the above clearly defined calrifications, in FSA 200136010, the conlusion arrived at by the Service was that a bank must capitalize the expenditure involved in acquisition of credit card receivables. It includes also credit card accounts from other institutions. In this connection the bank had in its return "deducted the cost of acquiring and securitizing the credit card receivables" ( David J 2002), which the tax officer disallowed. On appeal by the bank against the deductions, it was pointed out that in the case of INDOCO Inc, 503 US 79 (1992), the IRS had already decided that credit card receivables were assets capable of giving future benefits along with interst.and that IRS further decided that it could not be amortized also under sec 195 which only provided for investigative expenses for starting a buisness and not for purchasing a partcular capital asset in reply to the contention of the bank that the expnses were of investigatory in nature and could therfore b e deducted. Under the circumstances, it is

To What Extent Do You Think Was a Revolutionary Sculptor Essay Example for Free

To What Extent Do You Think Was a Revolutionary Sculptor Essay Kritios was an Athenian sculptor, whose style and technique during the late archaic period helped revolutionize the archaic period into the Classical period. He has two main statutes that I am going to examine the first of which being the Kritios boy. Also referred to as â€Å"the first beautiful nude art† it is very important as it is a precursor to the later classical sculptures. It depicts a young boy in an idea form (so sculpted in the nude if they where in the ideal form) and is possibly a reflection of the Athenian cultural obsession with Pederasty. Yet it is more important in the sense that it smashes the Korous pose. The Kritios boy is so important as Kritios has mastered a complete understanding of how the different parts of the body act together, the statue supports the weight on the left leg meaning that the right one is bent at the knee and relaxed, and forces a chain of events as the pelvis is pushed diagonally upwards on the left side this causes the right buttock to relax and the spine to be placed in an â€Å"S† shaped curve causing the shoulder line to dip left to counteract the action of the pelvis. his stance is referred to as contrapposto, and the Kritios boy is one of the earliest examples of it mastered. (One of the greatest examples of contrapposto in history was during the neoclassical period ‘David† by Michelangelo, 1504) but this could not have been achieved without Kritios. The kritios boy also shows a number of other innovations that distinguish it from any of the Archaic Kouroi or anythi ng from the Archaic period. The muscular and skeletal structure are depicted with an unforced life-like accuracy as well as having the rib cage naturally expanded. Almost as if he is breathing in. the statue’s hips are relaxed and another reason why it is revolutionary in the break though into the classical period is the â€Å"smile† of the archaic statues, has been changed to accurate lips and the face is completely emotionless. The second Kritios statue I am going to look at was not just made by him, He and Nesiotes combined their sculptures of Aristogeiton and Harmodius to make ‘The Tyrannicides’ (477-476BC). These statues were a replica of the climax of the story about the two men who killed the Tyrant Of Athens. The Tyrannicides story is told through their stances and the objects they were holding. Aristogeiton (Eromenos); the statue sculpted by Kritios was the older man and the one with all the experience and wisdom who has a beard. He managed to show this by the way Aristogeiton was standing with one leg in front of the other at a defence angle. His arm flat out holding a knife to show his weapon. That he used to stab Hippias to death, some drapery over his arm is shown, and it appears to be being used as some kind of defense, this illustrates that he is experienced. Once again Kritos has used details and the realism to help push sculptor and realism forward with Aristogeiton’s muscles, stance, facial features. As well as beard that course stands out (again illustrating how he is wise). Both statues have frontal emphasis with both having a leg in front and their attacking arms pointing out to the front. The use of frontal emphasis almost puts you in Hipparchus’ shoes because it is what he would have seen when he was getting attacked. Making this a very threatening and violent image. Aristogeiton’s partner Harmodius was sculpted by Nesiotes who followed Kritios’ example and decided to base Hamodius on the opposite of Aristogeiton and make him extremely inexperienced and reckless. Because of his youth, he lacked the experience that Aristogeiton had, therefore his pose was very reckless and he is open to be attacked as his arm in the air exposing the rest of his body,. These men were seen as heroes for the way they killed the King who was more of a tyrant, which opened up Athenian democracy. And they have been immortalized and shown as very strong powerful figures. Again the statues are both very realistic in the way all the joints and body work together (the fact more weight is on one left leg this causes the pelvises to rise ect) In conclusion I feel that Kritios was a revolutionary sculptor as he mastered how a human figure standing with most of it’s weight on one foot causes a compelete change throughout the body as the human form does causing his statues to look allot more realist. This caused a massive step forward in the art and ability to create lifelike sculptures that completely makes the stiff kouroi of the archaic period completely obsolete.

The Limitations Of 4G

The Limitations Of 4G Although the concept of 4G communications shows much promise, there are still limitations that must be addressed. One major limitation is operating area. Although networks are becoming more ubiquitous, there are still many areas not served. Rural areas and many buildings in metropolitan areas are not being served well by existing wireless networks. This limitation of todays networks will carry over into future generations of wireless systems. The hype that is being created by 3G networks is giving the general public unrealistic expectations of always on, always available, anywhere, anytime communications. The public must realize that although high-speed data communications will be delivered, it will not be equivalent to the wired Internet at least not at first. If measures are not taken now to correct perception issues, 4G services are deployed, there may be a great deal of disappointment associated with the deployment of the technology, and perceptions could become negative. If thi s were to happen, neither 3G nor 4G may realize its full potential. Another limitation is cost. The equipment required to implement a next generation network is still very expensive. Carriers and providers have to plan carefully to make sure that expenses are kept realistic. Some issue expected with the implementation of 4G with multiple heterogeneous networks are issues such as; †¢ access, †¢ handoff, †¢ location coordination, †¢ resource coordination to add new users, †¢ support for multicasting, †¢ support for quality of service, †¢ wireless security and authentication, †¢ network failure and backup, and †¢ pricing and billing. Network architectures will play a key role in implementing the features required to address these issues. POSSIBLE ARCHITECTURES One of the most challenging problems facing deployment of 4G technology is how to access several different mobile and wireless networks. Figure 1 shows three possible architectures: using a multimode device, an overlay network, or a common access protocol. Multimode devices One configuration uses a single physical terminal with multiple interfaces to access services on different wireless networks. Early examples of this architecture include the existing Advanced Mobile Phone System/Code Division Multiple Access dual-function cell phone, Iridiums dual function satellite-cell phone, and the emerging Global System for Mobile telecommunications/Digital Enhanced Cordless Terminal dual-mode cordless phone. The multimode device architecture may improve call completion and expand effective coverage area. It should also provide reliable wireless coverage in case of network, link, or switch failure. The user, device, or network can initiate handoff between networks. The device itself incorporates most of the additional complexity without requiring wireless network modification or employing interworking devices. Each network can deploy a database that keeps track of user location, device capabilities, network conditions, and user preferences. The handling of quali ty-of-service (QoS) issues remains an open research question. Overlay network In this architecture, a user accesses an overlay network consisting of several universal access points. These UAPs in turn select a wireless network based on availability, QoS specifications, and userdefined choices. A UAP performs protocol and frequency translation, content adaptation, and QoS negotiation-renegotiation on behalf of users. The overlay Issues in network, rather than the user or device, performs handoffs as the user moves from one UAP to another. A UAP stores user, network, and device information, capabilities, and preferences. Because UAPs can keep track of the various resources a caller uses, this architecture supports single billing and subscription. Common access protocol This protocol becomes viable if wireless networks can support one or two standard access protocols. One possible solution, which will require interworking between different networks, uses wireless asynchronous transfer mode. To implement wireless ATM, every wireless network must allow transmission of ATM cells with additional headers or wireless ATM cells requiring changes in the wireless networks. One or more types of satellite-based networks might use one protocol while one or more terrestrial wireless networks use another protocol. QUALITY OF SERVICE Supporting QoS in 4G networks will be a major challenge due to varying bit rates, channel characteristics, bandwidth allocation, fault-tolerance levels, and handoff support among heterogeneous wireless networks. QoS support can occur at the packet, transaction, circuit, user, and network levels. †¢ Packet-level QoS applies to jitter, throughput, and error rate. Network resources such as buffer space and access protocol are likely influences. †¢ Transaction-level QoS describes both the time it takes to complete a transaction and the packet loss rate. Certain transactions may be timesensitive, while others cannot tolerate any packet loss. †¢ Circuit-level QoS includes call blocking for new as well as existing calls. It depends primarily on a networks ability to establish and maintain the end-to-end circuit. Call routing and location management are two important circuit-level attributes. †¢ User-level QoS depends on user mobility and application type. The new location may not support the minimum QoS needed, even with adaptive applications. In a complete wireless solution, the end-to-end communication between two users will likely involve multiple wireless networks. Because QoS will vary across different networks, the QoS for such users will likely be the minimum level these networks support. End-to-End QoS Developers need to do much more work to address end-to-end QoS. They may need to modify many existing QoS schemes, including admission control,dynamic resource reservation, and QoS renegotiation to support 4G users diverse QoS requirements. The overhead of implementing these QoS schemes at different levels requires careful evaluation. A wireless network could make its current QoS information available to all other wireless networks in either a distributed or centralized fashion so they can effectively use the available network resources. Additionally, deploying a global QoS scheme may support the diverse requirements of users with different mobility patterns. The effect of implementing a single QoS scheme across the networks instead of relying on each networks QoS scheme requires study. Handoff delay Handoff delay poses another important QoS-related issue in 4G wireless networks. Although likely to be smaller in intranetwork handoffs, the delay can be problematic in internetwork handoffs because of authentication procedures that require message exchange, multiple-database accesses, and negotiation-renegotiation due to a significant difference between needed and available QoS. During the handoff process, the user may experience a significant drop in QoS that will affect the performance of both upper-layer protocols and applications. Deploying a priority-based algorithm and using location-aware adaptive applications can reduce both handoff delay and QoS variability. When there is a potential for considerable variation between senders and receivers device capabilities, deploying a receiver-specific filter in part of the network close to the source can effectively reduce the amount of traffic and processing, perhaps satisfying other users QoS needs. Although 4G wireless technology of fers higher bit rates and the ability to roam across multiple heterogeneous wireless networks, several issues require further research and development. It is not clear if existing 1G and 2G providers would upgrade to 3G or wait for it to evolve into 4G, completely bypassing 3G. The answer probably lies in the perceived demand for 3G and the ongoing improvement in 2G networks to meet user demands until 4G arrives.

The lost boy :: essays research papers

  Ã‚  Ã‚  Ã‚  Ã‚  `  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Abbie Rader Title: The lost boy Author: Dave Pelzer Publisher: Health Communications, Incorporated Publication Date: September 1997 Number of pages: 250   Ã‚  Ã‚  Ã‚  Ã‚  Lost boy is a follow up to Dave Pelzer’s book A Child Called It. This Novel Is a Auto-biography by Dave Pelzer. It follows his experiences in the foster care system. After being taken from his mother Dave goes from one foster home to another and he describes his life there.   Ã‚  Ã‚  Ã‚  Ã‚  The Novel starts out where it left off in the novel A Child called â€Å"It† which is his mother as always abusing him. To better knowledge you on this book the first paragraph of this novel reads ( I’m alone. I’m hungry and I’m shivering in the dark. I sit on top of my hands at the bottom of the stairs in the garage. My head is tilted backward. My hands became numb hours ago. My neck and shoulder muscles begin to throb. But that’s nothing new- I’ve learned to turn off the pain. I’m Mother’s prisoner.) This nine years old boy was treated worse then the animals he lived with. He was told when to move, when to eat, and when he was aloud to sleep. This novel takes you threw him being taken from his mother which made him a ward of the state to going threw series of foster family and also in a juvenile detention center.   Ã‚  Ã‚  Ã‚  Ã‚   I think that everyone in the world should read this book because it is a very indebt novel. Any one that wants to pursue a career dealing with child abuse or anything related to it should also read this book so they can see a abused child’s point of view. The main reason that I love this book dearly is because it is a very emotional novel and also because it really metaphorically put you in Dave’s life situations.

Character Growth in Conrads Heart of Darkness Essay -- Heart of Darkne

Character Growth in Conrad's Heart of Darkness      Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   Joseph Conrad's Heart of Darkness explores the intellectual, emotional and moral growth of characters throughout the novella. This character growth has been a recurring theme in literature, with the poet William Blake, among many others, exploring theories of the movement between innocence to experience. Although Conrad does not strictly address character growth in this manner, characters that do and do not undergo psychological growth are portrayed quite differently. Those who undergo these psychological changes are portrayed favorably, that is Marlow, the frame narrator, and Kurtz. These characters throughout the novel undergo significant change, for some it is gradual (Marlow), but for others such as Kurtz, this growth or realization occurs rapidly, and almost too late. While European colonialists - characters that do not grow, or remain at the stagnant psychological level - are used to represent the anti-colonialism theme to the readers. Conrad utilizes c haracters, and their psychological growth (or lack of growth) to distance himself from the narrative and endorse or criticize many themes that would be seen as revolutionary in the context of its publication. A large gap is then depicted between the characters who grow, portrayed as "enlightened" beings, and the pilgrims and European colonialists, who are seen in a colonial point of view as perfect examples of good, however portrayed by Conrad as stagnant, "Hollow men", whose aims and ideals are criticized.       The frame narrator, although not a major character in the novella, undergoes significant psychological growth throughout the text. This growth can be broadly divided into three phases - the initia... ...hed ways of thinking, have a faà §ade of bringing culture and progress to a world devoid of these elements, yet are merely "hollow men". They are merely acting as products for the indefinable aims of colonialism and in turn, move the readership to reject their ideals, emphasize the "enlightened" (those who grow) and encourage a similar psychological journey of the readership.          Bibliography    Conrad, J. (1995). Heart of Darkness. London: Penguin Group.    Dintenfass, M. (1996, March) Heart of Darkness Lecture. [WWW document]  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   URL http://www.lawrence.edu    Maes-Jelinek, H. Notes on Heart of Darkness    Moon, B. (1992). Literary Terms A practical Glossary. Perth: Chalkface Press P/L    Analysis of Major Characters. [WWW document]  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚  Ã‚   URL http://www.sparknotes.com/lit/heart/characteranalysis.htm      

Time to Digital Converter Used in All Digital Pll

Master Thesis ICT Time to Digital Converter used in ALL digital PLL Master of Science Thesis In System-on-Chip Design By Chen Yao Stockholm, 08, 2011 Supervisor: Dr. Fredrik Jonsson and Dr. Jian Chen Examiner: Prof. Li-Rong Zheng Master Thesis TRITA-ICT-EX-2011:212 1 ACKNOWLEDGEMENTS I would like to thank: Professor Li-Rong Zheng for giving me the opportunity to do my master thesis project in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the overall research and plan. Dr.Jian Chen for answering all my questions and making the completion of the project possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions during the thesis work. My mother Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me. i ABSTRACT This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters.Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442 µW with 1. 2V power supply. Measured integral nonlinearity and differential nonlinearity are 0. LSB and 0. 33LSB respectively. Keywords: All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), Current Starved, Vernier delay line ii Contents ACKNOWLEDGEMENTS †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. i LIST OF FIGURES†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. iv LIST OF TABLES †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1. 2. Introduction †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚ ¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 1 State of art †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 4 2. 1 2. 2 2. 3 2. 4 3 Buffer delay line TDC†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 4 Inverter delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. Vernier TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 5 Gated ring oscillator (GRO) TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 6 System level design †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 7 3. 1 3. 2 3. 3 3. 4 Goal †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 9 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 10 Performance comparison †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 11 4 Schematic design and simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 12 4. 1 Sense Amplifier Based Flip-Flop â € ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 2 Schematic design†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 14 Sampling window simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 16 4. 1. 1 4. 1. 2 4. 2 Vernier delay line TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦. 21 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 21 Simulation results †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 5 4. 2. 1 4. 2. 2 4. 3 Parallel TDC †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Delay cells †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 28 Simulation results †¦Ã¢â‚¬ ¦Ã¢â ‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 30 4. 3. 1 4. 3. 2 5 Layout and post-simulation†¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 3 5. 1 5. 2 5. 3 Layout of SAFF and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 33 Layout of parallel TDC and post-simulation †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 35 Comparison and analysis †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã ¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 38 6 7 8 Conclusion †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦ 0 Future work †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 41 Reference †¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦Ã¢â‚¬ ¦.. 42 iii LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 iv Effect of LO phase noise in transmitter Block diagram of the phase-domain ADPLL frequency synthesizer Retiming of the reference clock signal (FREF) Operating principle of time-to-digital converter Buffer delay line TDC Inverter delay line TDC Vernier delay line TDC Gated ring oscillator TDC Test bench for measuring rising/falling time of input of TDC Input and output of inverter Diagram of Vernier delay line TDC Timing of the interfaces of Vernier TDC Diagram of parallel TDC Timing of the interfaces o f parallel TDC Symmetric SAFF Schematic of SAFF Schematic of Sense Amplifier Schematic of symmetric SR latch Test bench of SAFF Normal Sampling Case Extreme case of sampling for setup time simulation Extreme case of sampling for hold time simulation Sampling window simulation Current starved delay element Schematic of Matched delay cell Schematic of delay cell 1 Schematic of delay cell 2 Schematic of Vernier delay line TDC Input of Vernier TDC (stop – start) = 0ps Input of Vernier TDC (stop – start) = 20ps Vernier TDC transfer function Vernier TDC linearity Monte Carlo simulation of the resolution for Vernier delay line TDC Delay cell in Parallel TDC Delay time Vs width of transistor T5 Schematic of Parallel TDC Input of parallel TDC (stop – start) = 0ps Input of parallel TDC (stop – start) = 20ps Parallel TDC transfer function Parallel TDC linearity Floor Plan of SAFF Layout of SAFF Post-simulation of sampling window Floor plan of Clock distribution Layo ut of parallel TDC Figure 46 Figure 47 Figure 48 Figure 49 Input of parallel TDC after layout (stop – start) = 0ps Input of parallel TDC after layout (stop – start) = 30ps Parallel TDC transfer function after layout Parallel TDC linearity after layout LIST OF TABLES Table 1 Table 2 Performance comparison between Vernier TDC and parallel TDC Comparison to previous work v 1.Introduction All digital phase locked loop (ADPLL) is employed as frequency synthesizer in radio frequency circuits to create a stable yet tunable local oscillator for transmitters and receivers due to its low power consumption and high integration level. It accepts some frequency reference (FREF) input signal of a very stable frequency of and then generates frequency output as commanded by frequency command word (FCW). The desired frequency of output signal is an FCW multiple of the reference frequency. For an ideal oscillator operating at all power is concentrated around , but the spectrum spreads i nto nearby frequencies in practical situation.This spreading is referred as phase noise which can cause interference in adjacent bands in transmitters and reduce selectivity in receivers [1]. Fig. 1. Effect of LO phase noise in transmitter [1] For example, shown as Fig. 1, when a noiseless receiver must detect a weak desired signal at frequency in the presence of a powerful nearby transmitter generating at frequency with substantial phase noise, the desired signal will be corrupted by phase noise tails of transmitter. Thus the modern radio communication systems require strict specifications about phase noise of synthesizers. In the ADPLL, the time to digital converter (TDC) serves as the phase frequency detector (PFD) meanwhile the digitally controlled Oscillator (DCO) replaces the VCO.The core module is DCO which deliberately avoids analog tuning voltage controls. The DCO is similar to a flip flop whose internal is analog but the analog nature does not propagate beyond the boundari es. Compared to the analog PLL, the loop filter can be implemented in a fully digital manner which will save a large amount of area and maintain low power consumption. 1 Fig. 2. Block diagram of the phase-domain ADPLL frequency synthesizer [2] Fig. 2 shows a type II ADPLL which includes two poles at zero frequency. It has better filtering capabilities of oscillator noise compared to type I ADPLL, leading to improvements in the overall phase noise performance. The ariable phase signal is determined by counting the number of rising clock transitions of the DCO oscillator clock. The reference phase signal is obtained by accumulating the Frequency Command Word (FCW) with every rising edge of the retimed Frequency Reference (FREF) clock. The sampled variable phase is subtracted from the reference phase in a synchronous arithmetic phase detector which is defined by = + ? [k] [2]. Fig. 3. Retiming of the reference clock signal (FREF) [3] 2 There are two asynchronous clock domains, FREF and CKV, and it is difficult to compare the two digital phase values physically at different time instances without facing the metastability problem.During frequency acquisition, their edge relationship is not known, and during phase lock, the edges will exhibit rotation if the fractional FCW is nonzero [1]. Therefore, it is imperative that the digital-word phase comparison should be performed in the same clock domain. This is achieved by retiming process which is performed by oversampling the FREF clock with CKV for synchronization purpose (fig. 3). The retimed clock, CKR is used to synchronize the internal ADPLL operations. However, the retiming process generates a fractional phase error in CKV cycles which is estimated by TDC [3]. The DCO produces phase noise at high frequency, while the TDC determines the in band noise floor [4].The noise contribution of TDC within the loop bandwidth at output of ADPLL is where denotes the delay time of a delay cell in the TDC chain, is the period of RF output and is the frequency of the reference clock [1]. The equation above indicates that a smaller leads to smaller quantization noise from TDC. As a result, the effort is devoted to achieve high resolution TDC in order to obtain low phase noise of ADPLL. Fig. 4. Operating principle of time-to-digital converter [5] Fig. 4 illustrates the principle of time-to-digital converter based on digital delay line. The start signal is delayed by delay elements and sampled by the arrival of the rising edge of stop signal.The sampling process which can be implemented by flip-flops freezes the state of delay line as the stop signal occurs. The outputs of flip-flop will be high value if the start signal passes the delay stages and the sampling process will generate low value if the delay stages have not been passed by start signal. As a result, the position of high to low transition in this thermometer code indicates how far the start signal can be propagated in the interval spanned by star t and stop signal. 3 2. State of art 2. 1 Buffer delay line TDC Fig. 5. Buffer delay line TDC [5] The start signal ripples along the buffer chain and flip-flops are connected to the outputs of buffers. On the arrival of stop signal the state of delay line is sampled by flip-flops.One of the obvious advantages of this TDC is that it can be implemented fully digital. Thus it is simple and compact. However, the resolution is relatively low since it is the delay of one buffer. 2. 2 Inverter delay line TDC Fig. 6. Inverter delay line TDC [5] The resolution in this TDC is the delay of one inverter which is doubled compared to buffers delay chain. In this case, the length of measurement intervals is not indicated by the position of high to low transition but by a phase change of the alternation of high to low sequence. Consequently, the rise and fall delay of inverter should be made equal which requires highly 4 match of the process.In addition, the resolution is still limited by technolog y and therefore not high enough in our application of ADPLL. 2. 3 Vernier TDC Fig. 7. Vernier delay line TDC [6] Vernier delay line TDC is capable of measuring time interval with sub-gate resolution. It consists of two delay lines which delay both start signal and stop signal. The delay in the first line is slightly larger than the delay in the second line. During the measurement, the start signal propagates along the first line and the stop signal occurs later. It seems like the stop signal is chasing start signal. In each stage, it catches up by = Delay1- Delay2 Therefore the resolution is dependent on the difference of two delay stages instead of one delay element.Although the Vernier delay line TDC improves the resolution effectively, the area and power consumption is increased dramatically as the dynamic range becomes larger due to that each stage costs two buffers and one flip-flop. Besides, the conversion time will be increased and in a result it might be not feasible to work in a system. 5 2. 4 Gated ring oscillator (GRO) TDC Fig. 8. Gated ring oscillator TDC [6] The GRO TDC could achieve large dynamic range with small number of delay elements. It measures the number of delay element transitions during measurement interval. By preserving the oscillator state at the end of the measurement interval [k? ], the quantization error [k? 1], from that measurement is also preserved. In fact, when the following measurement of [k? 1] is initiated, the previous quantization error is carried over as [k] = [k? 1]. This results in first-order noise shaping of the quantization error in the frequency domain. Apart from the quantization noise, according to the well-known barrel shift algorithm for dynamic element matching, GRO TDC structure realizes first order shaping of mismatch error [6]. Thus, we can expect that this architecture ideally achieve high resolution without calibration even in the presence of large mismatch. 6 3 System level design 3. 1 GoalThe proposed TDC is designed to work with a 5GHz DCO and a 20MHz reference input while the circuit is fabricated in 65nm IBM CMOS technology; the supply voltage is 1. 2V and development environment is Cadence 6. 1. 3. Fig. 9. Test bench for measuring rising/falling time of input of TDC In order to find out the rising/falling time of the input signal for TDC, the 5GHz sine wave signal which is the same as the output of DCO in ADPLL is put through the inverter with the smallest size and the rising/falling time of the output of inverter is measured (Fig. 9) . 7 Fig. 10. Input and output of inverter Rising/falling time = 16. 58ps. This value is applied to model the practical case of input signals for TDC.The purpose for putting the sinusoid signal generated from DCO passing through the smallest inverter is to model the worst case for TDC with weakest driving ability. As the system level simulation result of ADPLL presents, the dynamic range of TDC is 20ps. The converter resolution is required to be around 2ps meanwhile the power consumption should be kept as low as possible. Since in the application of this ADPLL, sub-gate resolution and small dynamic range are targeted, two kinds of topologies of TDC are proposed. One is Vernier delay line TDC and the other one is parallel TDC. The comparison of these two architectures is concluded and both of them are designed on schematic level. 8 3. 2 Vernier delay line TDCStart Matched delay cell1 EN EN_ Delay1 Delay1 Delay1 Start_ Matched delay cell1 D Q D_ CLK Delay1 D Q0 D_ CLK Delay1 Delay1 D Q26 D_ CLK Stop Fig. 11. Diagram of Vernier delay line TDC 200ps Matched delay cell2 Delay2 Delay2 Delay2 start 20ps stop enable Valid output 2ns TDC_output Fig. 12. Timing of the interfaces of Vernier TDC As the description about Vernier TDC before, the start signal and stop signal are propagated by two delay line with small delay difference each stage respectively. The clock gating technology controlled by enable signal is used to realize low p ower dissipation. The timing relationship of interfaces is described in Fig. 2 which indicates that enable signal should be set to high value half 9 cycle of start signal ahead of the stop rising edge and the conversion time is about 2ns. The delay time of each stage in TDC is about 60ps to 70ps and 27 stages are design to cover the whole dynamic range so that the conservative estimation of conversion time of TDC would be no more than 2ns. The next stage of TDC in ADPLL should sample the output when it is stable. Since the period of FREF is 50ns which means that the instance of measurement occur every 50ns, it is reasonable to adopt the method of serial conversion and prepare the valid output data after 2ns delay. 3. 3Parallel TDC Start Current Staved delay cell EN EN_ Start_ Current Starved delay cell D Q0 D_ CLK Stop Fig. 13. Diagram of parallel TDC Delay1 Delay2 Delay12 D Q1 D_ CLK D Q11 D_ CLK 10 200ps 20ps start stop enable Valid output 420ps TDC_output Fig. 14. Timing of the i nterfaces of parallel TDC Configuring the gates not in a chain but in parallel generates TDC depicted in Fig. 13. The start signal applied to all delay elements in parallel. On the rising of stop signal the outputs of all delay elements are sampled at the same time. Instead of propagating the differential start signal, stop signal is delayed to avoid differential mismatch problem.The delay cells connected to stop signal are sized for delays = 0+? ?N =? . The time difference between the delayed stop signal is quantized with a resolution The conversion results are available immediately after the rising of stop signal. 3. 4 Performance comparison Parallel TDC Parallel delay elements with gradually increasing propagation delays are simultaneously sampled on the arrival of stop signal. No loop structure feasible Sub-gate resolution Conversion time independent from resolution Susceptible to variations Not feasible to high dynamic range Careful layout design Vernier TDC Principle Start and stop signals propagate along two delay lines with slightly different delays.Loop structure Pros Loop structure possible Sub-gate resolution Modular structure High dynamic range possible with loop structure Differential delay lines Conversion time depends on measurement interval and resolution Cons Table1. Performance comparison between Vernier TDC and parallel TDC 11 4 Schematic design and simulation 4. 1 Sense Amplifier Based Flip-Flop Flip-Flops are critical to the performance of Time to Digital Converter due to the tight timing constraints and low power requirements. Metastability is a physical phenomenon that limits the performance of comparators and digital sampling elements, such as latches and flip-flops. It recognizes that it akes a nonzero amount of time from the start of a sampling event to determine the input level or state [15]. This resolution time gets exponentially larger if the input state change gets close to the sampling event. In the limit, if the input changes a t exactly the same time as the sampling event, it might theoretically take an infinite amount of time to resolve. During this time, the output can dwell in an illegal digital state somewhere between zero and one. However, this flip flop is supposed to be reused in ADPLL so that the metastable condition of the retimed reference clock CKR is not acceptable. One reason is that the metastability of any clock could introduce glitches and double clocking in the digital logic circuitry being driven.The other reason is that it is quite likely that within a certain metastability window between FREF and CKV, the clock to Q delay of the flip flop would have the potential to make CKR span multiple DCO clock periods. This amount of uncertainty is not acceptable for proper system operation [4]. For the application of TDC, due to that the metastability sampling window should be no larger than the high resolution to avoid bubbles in TDC code [7], sensed amplifier based flip-flop (SAFF) is chosen. 1 2 VDD MP1 MP2 MP3 MP4 MN3 VDD MN4 D MN1 MN5 MN2 D_ CLK MN6 Pulse Generator Symmetrical SR latch S_ S R VDD R_ MP7 MP8 MP5 MP6 MP9 Q MP10 Q_ MN9 MN10 MN7 MN11 MN12 MN8 Fig. 15. Symmetric SAFF The SAFF shown as Fig. 5 consists of sense amplifier in the first stage and SR latch in the second stage. The amplifier senses complementary differential inputs and produces monotonous transitions from high to low logic level on one of the outputs following the leading clock edge. The SR latch captures each transition and holds the state until the next leading clock arrives [8]. When CLK is low, S_ and R_ are charged to high level through MP1 and MP4 meanwhile MN6 is closed. If D is high, S_ will be discharged through MN3, MN1 and MN6 which is opened by clock leading edges. Accordingly, R_ is hold to high level and Q is high in this case. The additional transistor MN5 is used to provide the discharging patch to ground. For example, when 13 ata is changed as CLK is high which means D is low and D _ is high at this time, S_ would be charging to high level if there is no MN5. However, S_ could be discharged through MN3, MN5, MN2 and MN6 since MN5 provides another path to ground. Although SR latch is able to lock the state of outputs of sense amplifier, MN5 prevents potential charging caused by leakage current even after the input data is changed and therefore guarantee the stable outputs of flip-flop. The SR latch, as the output stage, is kind of symmetric topology with equivalent pull-up and pulldown transistors network. Q+ = S + R_ ·Q Q_+ = R + S_ ·Q_ In the equations above, Q represents a current sate and Q+ represents a future state after the transition of clock.Thus this circuit has equal delays of outputs and provides identical resolution of the rising and falling meta-stability of their input data. In addition, the data input capacitive loading is only one NMOS transistor and the interconnect capacitance parasitic is minimized. 4. 1. 1 Schematic design The basic pri nciples of the SAFF design are that the size of the input transistors should be small enough to minimize the load effect of SAFF and large enough to ensure the speed of it. The PMOS and NMOS networks should be matched and the sizes of transistors are adjusted to obtain equal delay of differential outputs. Fig. 16. Schematic of SAFF 14 Fig. 17. Schematic of Sense Amplifier Fig. 18. Schematic of symmetric SR latch 15 4. 1. 2 Sampling window simulation Fig. 19.Test bench of SAFF The ideal switch is used to initialize the output signal Q otherwise Q will be floating at the beginning of simulation which would result in unpredictable rising or falling edge at the beginning therefore make it difficult to measure a fixed number of signal transition edge. In the practical case, the initial value of inputs of flip flop is either zero or one. The simulation is performed by tuning the delay time of CLK in order to change the time interval between CLK and D/D_. There are several cases simulated to verify the timing constraints of SAFF including setup timing, hold timing and sample window. 1. Normal sampling 16 Fig. 20. Normal Sampling Case Data D changes from zero to one and then is sampled after it is stable for a while. The crossing point of Q and Q_ is around 600mV which means there are equal delay of clock to Q and clock to Q_ due to the symmetric topology of SAFF. 2.Setup time simulation Setup time is the minimum time prior to triggering edge of the clock pulse up to which the data should be kept stable at flip flop input so that data could be properly sampled. This is due to the input capacitance present at the input. It takes some time to charge to the particular logic level at the input. During the simulation, the input data is changing from low to high and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 17 Fig. 21. Extreme case of sampling for setup time simulation The clock to Q delay is incre asing exponentially when input data is approaching the clock triggering edge.When the data comes later than clock edge for 15ps, the clock to Q delay is up to about 280ps shown in Fig. 21. If the data comes even later than this, the output of flip flop will enter into metastable state or will never output high value. 3. Hold time simulation Hold time is the minimum time after the clock edge up to which the data should be kept stable in order to trigger the flip flop at right voltage level. This is the time taken for the various switching elements to transit from saturation to cut off and vice versa. During the simulation, the input data is changing from high to low and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 18 Fig. 22.Extreme case of sampling for hold time simulation The clock to Q delay is increasing exponentially if transition of input data from one to zero happens close to the clock edge. As long as t he data could keep stable long enough the flip flop is capable of recognizing it during limit time interval. The hold timing constraint is that data should be stable after the clock rising at least 16ps (Fig. 22) to guarantee flip-flop could sample the right value otherwise the flip flop will enter into illegal state or never output high value. 4. Sampling window 19 2. 9 2. 8 2. 7 2. 6 x 10 -10 Tclk-Q 2. 5 setup time 2. 4 2. 3 2. 2 2. 1 2 -0. 5 hold time 0 0. 5 1 1. 5 2 Tdata-clk 2. 5 3 3. 5 x 10 4 -11 Fig. 23. Sampling window simulationSampling window is defined as the time interval in which the flip-flop samples the data value. During the interval any change of data is prohibited in order to ensure robust and reliable operation [8]. The flip-flop delay increases as the signal approaches the point of setup and hold time violation until the flip-flop fails to capture the correct data [9] which is displayed in Fig. 23. Metastability is modeled in critical flip-flops by continuous ins pection of the timing relationship between the data input and clock pins and producing an unknown output on the data output pin if the delay to clock skew falls within the forbidden metastable window. Referring to Fig. 3, the metastable window is defined as an x-axis region such that the clock to Q delay on the y-axis is longer by a certain amount than the nominal clock to Q delay. For example, if the nominal clock to Q delay is 200ps when the data to clock timing is far from critical, the metastability window would be 15ps if one can tolerate clock to Q delay increase by 20ps. If one can tolerate a higher clock to Q delay increase of 30ps, the metastable window would drop to 6 ps. A question could be asked as to how far this window can extend. The limitation lies in the fact that for a tight data to clock skew, the noise or other statistical uncertainty, such as jitter, could arbitrarily resolve the output such that the input data is missed.Therefore, for a conventional definition of setup time, not only must the output be free of any metastable condition, but the input data have to be captured correctly. For this reason, the setup and hold times are conservatively defined in standard-cell libraries for an output delay increase of 10 or 20% over nominal. The specific nature of TDC vector capturing does not require this restrictive constraint. Here, any output-level resolution is satisfactory for proper operation as long as it is not metastable at the time of capture, and consequently, 20 the metastable window could be made arbitrarily small [1]. This SAFF demonstrates very narrow sampling window less than 1ps according to the simulation results. 4. 2Vernier delay line TDC There are several components in Vernier delay line TDC including inverter, SAFF, matched delay cell, delay cell 1 and delay cell 2 in which matched delay cell has the same circuit topology with other two delay cells except that it has enable control pins. 4. 2. 1 Delay cells There are severa l methods to implement delay elements. The most popular three methods for designing variable delay cells are shunt capacitor technique, current starved technique and variable transistor technique [10]. In this thesis project, current starved delay element is employed because of its simple structure and relatively wide delay range of regulation.Vdd VBP M4 M2 M6 Vdd in C M1 M5 out VBN M3 Fig. 24. Current starved delay element As can be seen from the Fig. 24, there are two inverters between input and output of this circuit. The charging and discharging currents of the output capacitance of the first inverter, composed of M1and M2, are controlled by the transistors M3 and M4. Charging and discharging currents depend on the bias voltage of M3 and M4 respectively. In this delay element, both rising and 21 falling edges of input signal can be controlled. By increasing/decreasing the effective on resistance of controlling transistor M3 and M4, the circuit delay can be increased /decreased.F ig. 25. Schematic of Matched delay cell As the enable signal is set to high level, the input signal will pass through this delay cell. The enable signal should be set to high level before the active edge of input signal comes. The differential start signal and stop signal passed through this delay cell to produce matched rising/falling edge signal for the next stage in TDC. With respect to design of the size of transistors, the input transistors of the delay cell should be relatively large to shield the load effect of SAFF meanwhile allow T5 to control the changing and discharging current through the capacitors of the first stage of inverter.The second stage of inverter should have enough driving ability for 5GHz input signals and therefore the sizes are specified large enough to withdraw sufficient current from power supply for transition. Due to that the differential signals are delayed, the delay cell is also required to have matched PMOS and NMOS networks to achieve equal delay time for rising or falling input signals. 22 Fig. 26. Schematic of delay cell 1 Fig. 27. Schematic of delay cell 2 23 The only difference between these two delay cells above is the size of transistor T5. The W/L ratio of T5 in delay cell 2 is a bit larger than delay cell 2 makes the delay of delay cell 2 is slightly shorter than delay cell 1. These two delay cells constitute two delay lines for Vernier TDC. Fig. 28.Schematic of Vernier delay line TDC This Vernier TDC includes 27 stages of delay cells for the reason that it should cover the dynamic range of 20ps and the additional offset value introduced by the setup timing of SAFF. The first dumpy stage of delay cell is used to match the differential input signals for the following delay lines so that the input signals for each stage are characterized with the same rising or falling time. As a result, the delay difference between each delay pair for start and stop signal is only dependent on the different size of transistors in the current starved delay cell. 24 4. 2. 2 Simulation results The input of Vernier TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps.The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 29. Input of Vernier TDC (stop – start) = 0ps Fig. 30. Input of Vernier TDC (stop – start) = 20ps 25 The offset value of this TDC is 8 observed from Fig. 29. The result shown in Fig. 30 indicates that the start signal has passed through 22 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (22 – 8) = 1. 43ps 25 20 Output of Vernier TDC (ps) 15 10 5 0 0 2 4 6 8 10 12 14 Input of Vernier TDC (ps) 16 18 20 Fig. 31. Vernier TDC transfer function 0. 6 0. 4 0. 2 DNL and INL [LSB] 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 INL DNL 0 2 4 6 8 10 12 Input of Vernier TDC 14 16 18 20 Fig. 32. Vernier TDC linearity 26The Differential Non Linearity (DNL) is the deviation in the difference between two successiv e threshold points from 1LSB. Integral Non Linearity (INL) is the deviation of the actual output. Both of them are calculated and reported in Fig. 32. The maximum DNL is +0. 4LSB while the maximum INL is -0. 89LSB. The process (skew) parameter files in the model directory contain the definition of the statistical distributions that represent the main process variations for the technology. This gives designers the capability of testing their designs under many different process variations to ensure that their circuits perform as desired throughout the entire range of process specifications. This is a Monte Carlo approach to the checking of designs.While being the most accurate test, it can also be time consuming to run enough simulations to obtain a valid statistical sample. Fig. 33. Monte Carlo simulation of the resolution for Vernier delay line TDC When running Monte Carlo to include FET mismatch, BOTH the Spectre mismatch and process vary statements are active. This will turn on b oth process and mismatch variations. Spectre provides the unique capability of running process variations independent of mismatch variations. This capability is not supported for this release. The average resolution calculated by averaging the delay difference between two delay lines is around 1. 66ps. The average power over one period is 148. 1E-6 W.The maximum power consumption is about 3. 6mW and the conversion time is around 2ns which is in accordance with the interfacing time estimation in system level design. Since the enable signal closed the TDC after the conversion is completed, the start signal with high frequency is prohibited to propagate so as to eliminate the unnecessary transition of delay cells and in a result saving the power dissipation. 27 4. 3 4. 3. 1 Parallel TDC Delay cells In order to design a serial of delay cells with the equal difference of delay time used in parallel TDC, the size of the transistor in a current starved structure is swept. Fig. 34. Delay ce ll in Parallel TDC 28Fig. 35. Delay time Vs width of transistor T5 Unlike Vernier TDC, only stop signal is delayed by various delay cells in parallel TDC. Thus the control of rising edge required, and then the size of transistor T5 is adjusted. As can be seen from Fig. 34, the size of transistors M1, M2, M4 and M5 is basically determined by the load capacitance which refers to the CLK pin of SAFF in this situation. Transistor T5 should be much smaller than M2 so that the discharging current could be controlled by T5. As the size of T5 increases, the delay time becomes smaller which means the delay cell is faster. According to the parameter analysis result in Fig. 5, the size of T5 can be determined by selecting the size corresponding to the delay time with 2ps difference for a serial delay cells. Fig. 36. Schematic of Parallel TDC 29 As the analysis in system level design, the delay cells are sized for delays = 0 + ? ?N. The single stop signal is delayed in parallel TDC, therefore t he matched delay cell connected to differential start signal is used to cancel the 0 and offset value. 4. 3. 2 Simulation results Similarly to Vernier TDC simulation, the input of parallel TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 37.Input of parallel TDC (stop – start) = 0ps 30 Fig. 38. Input of parallel TDC (stop – start) = 20ps The offset value of this TDC is 1 observed from Fig. 37. The result shown in Fig. 38 indicates that the start signal has passed through 11 stages of delay cells as the input is 20ps. Resolution = (20ps – 0ps)/ (11 – 1) = 2ps. 20 18 16 Output of parallel TDC (ps) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 Input of parallel TDC (ps) 16 18 20 Fig. 39. Parallel TDC transfer function 31 1 INL DNL DNL and INL [LSB] 0. 5 0 -0. 5 0 2 4 6 8 10 12 Input of parallel TDC 14 16 18 20 Fig. 40. Parallel TDC linea rity DNL and INL are calculated and reported in Fig. 40. The maximum DNL is +0. LSB while the maximum INL is 1LSB. The average power over one period is 87. 33E-6 W which is much smaller than Vernier TDC. The reason is that the clock gating technology controlled by enable signal eliminates the redundant transition of delay cells. As the system level design indicates, the parallel TDC only works for 420ps each period of stop signal because that the conversion is completed instantly due to the intrinsic characteristic of parallel TDC and therefore there is no power consumption during the rest time. Although the peak power consumption is approximately equivalent to Vernier TDC, the average power dissipation is decreased dramatically. 32 Layout and post-simulation 5. 1 Layout of SAFF and post-simulation For the layout of radio frequency circuit the interconnection parasitic will be a critical problem. In an audio application for instance parasitic will probably be a minor concern. Howeve r, the operation frequency of this circuit is 5GHz which means that the interconnection parasitic will influence the performance of circuit dramatically. To minimize this influence, we could move interconnections to higher metals and make the metals carry current rather than poly. Besides, the floor plan should be as compact as possible to optimize the parasitic and impedance of interconnections. GND T0Symmetric SR Latch T15 T14 T13 T8 T9 T5 T3 Q_ T1 T12 T10 T11 T7 Q T6 T4 T2 VDD T0 T2 T4 T3 T5 T9 T1 D T6 T7 D_ CLK T8 CLK GND Sensed Amplifier Fig. 41. Floor Plan of SAFF 33 There are several steps for floor plan. First step is to examine the size of transistors and split transistor size in a number of layout oriented fingers. Then identify the transistors than can be placed on the same stack according to the principles of using almost the same number of fingers per stack and put the transistors with common drain or source together. In the floor plan shown in Fig. 41, power line VDD i s reused by SR latch and sensed amplifier to make the connections compact.Fig. 42. Layout of SAFF 34 In the development environment of Cadence 6. 1. 3, Calibre is used for DRC and Assura is used to do LVS check and RCX. Post-simulation is then performed with av_extracted view. Fig. 43. Post-simulation of sampling window Compared to Fig. 23, Fig. 43 illustrates that the timing constraint point moved from 16ps to 29ps which will affect the offset value of TDC. In addition, the delay time from clock leading edge to output Q is increased. However, this SAFF after layout can be employed to avoid meta-stability effectively due to that the sampling window is still less than 1ps. 5. 2 Layout of parallel TDC and post-simulationIn this TDC system, the clock distribution network formed as a tree distributes the signal to all the delay cells. To reduce the clock uncertainty, the network requires highly matched topology showed as Fig. 44 below. 35 Clock Fig. 44. Floor plan of Clock distribution This kind of topology guarantees the equal delay from the common point clock to each element. Fig. 45. Layout of parallel TDC After DRC and LVS, the RC net list is extracted to do post-simulation. The input of parallel TDC after layout, the delay difference between the start and stop signal, is swept from 0 to 30ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 46.Input of parallel TDC after layout (stop – start) = 0ps 36 Fig. 47. Input of parallel TDC after layout (stop – start) = 30ps The offset value of this implemented TDC is 0 observed from Fig. 46. The result shown in Fig. 47 indicates that the start signal has passed through 10 stages of delay cells as the input is 30ps. Resolution = (30ps – 0ps)/ (10 – 0) = 3ps. 35 30 Output of parallel TDC after layout (ps) 25 20 15 10 5 0 0 5 10 15 20 Input of parallel TDC after layout (ps) 25 30 Fig. 48. Parallel TDC transfer function after layout 37 0. 5 0. 4 0. 3 DNL and INL after layout [LSB] 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 INL DNL 0 5 10 15 20 Input of parallel TDC (ps) 25 30 Fig. 49.Parallel TDC linearity after layout DNL and INL are calculated and reported in Fig. 49. The maximum DNL is 0. 33LSB while the maximum INL is 0. 5LSB. The average power over one period is 442. 1E-6 W. The maxim total current is about 3. 24mA. The peak power consumption is almost the same as the TDC before layout, but there are obvious ripples even the TDC is disabled due to that the parasitic capacitors increase the time for charging and discharging. 5. 3 Comparison and analysis Technique Parallel 2-level DL parallel Pseudo-diff DL VernierGRO CMOS [ µm] 0. 065 0. 35 0. 13 0. 09 0. 09 Supply [V] 1. 2 3 1. 2 1. 3 1. 2 Power [mW] 3. 89 50 2. 5 6. 9 4. 32 Resolution [ps] 3 24 12 17 6. 4 INL/DNL 0. 5/0. 3 -1. 5/0. 55 -1. 15/1 0. 7/0. 7 – Work This [12] [3] [7] [13] Table2. Comparison to previous work Table2 compares the proposed TDC to prior pub lished work in CMOS technology. This TDC features the fastest resolution with the best linearity. The power consumption is not directly comparable because the results from the other works are corresponding to different input range. However, it still indicates that this TDC consumes very low power due to that the start signal 38 only passes two buffers and the stop signal with low frequency is delayed. The TDC error has several components: quantization, linearity and randomness due to thermal effects.As can be seen from table5, the implemented TDC achieves medium linearity which can be improved if the layout is enhanced from floor plan considering the parasitic effects. With respect to quantization noise, the total noise power generated from this kind of TDC is spread uniformly over the span from dc to the Nyquist frequency without modulation. As a result, the proposed TDC contributes the lowest noise floor due to high resolution. = =3ps, , = 20MHz, we obtain = -104. 3 dBc/Hz. Banerj ee’s figure of merit (BFM) [14], being a 1-Hz normalized phase noise floor, is defined as BFM = where is a sampling frequency of the phase comparison and N= is the frequency division ratio of a PLL.It is used to compare the phase performance of PLLs with different reference frequencies and division ratios. In this TDC based ADPLL, BFM = -225. 3dB. Even though state-of-the-art conventional PLLs implemented in a SiGe process can outperform the ADPLL presented here in the in band phase noise, -213 dB in reference and -218 dB in reference, the worst case BFM of -205 dB appears adequate even for GSM applications, since there are no other significant phase-noise contributions as in the conventional PLLs [4]. However, the Gated Ring Oscillator TDC is able to push most of the noise to high frequency region which is then filtered by the loop filter in ADPLL through holding oscillation node state between measurements.The obvious drawback of this TDC is that the dynamic range is relativ ely small which will limit the application of it. Parallel TDC is not feasible to compose the loop structure so that the area and power dissipation will be increased dramatically if larger dynamic range is required. But the Vernier TDC designed in this thesis can be used in the loop structure for large dynamic range. 39 6 Conclusion In this thesis, two kinds of Time to Digital Converters are designed with Vernier and parallel structure on schematic level respectively. The performance of these two TDCs are concluded and compared. In the Vernier TDC, only two delay cells are designed and then reused to constitute two delay lines with slightly different delay time.This architecture is easy to implement and reduces the mismatch with delay cells. But the conversion time dependent on resolution and measurement interval time is relatively long since the signals are propagating along the delay cells in serial. On the other hand, in parallel TDC, the process of conversion is completed instan taneously due to that the signals are passing through the delay cells and then captured in parallel. Thus it has lower average power dissipation over one period. However, a set of delay cells are designed which obviously introduce nonlinearities. To minimize the mismatch problem, the single stop signal is delayed instead of two input signals for avoiding the differential mismatch situation.To sum up, both of the TDCs achieve sub-gate resolution which is able to meet the application requirements and Vernier TDC has higher resolution and better linearity but longer conversion time and larger power consumption compared to parallel TDC according to the simulation results. The parallel TDC is chosen to be implemented on layout. Comparing the results from schematic simulation and post-simulation, the performance is decreased on resolution, linearity and power consumption after layout. The major reason for this phenomenon is the parasitic capacitance of transistors and real wires which is a significant factor to affect the final properties in high frequency circuits.In the stage of schematic design, the sizes of transistors are not fully considered and results in difficulties on floor plan of layout. Specifically, the transistors are rather difficult to split into the same fingers per stack and therefore the floor plan is not compact enough to minimize the interconnections. Besides, the parasitic capacitance should have been emulated on schematic simulation in order to predict the effect after layout otherwise it would be very time consuming if the schematic design is modified after layout. In addition, the size of transistors is very small which makes them comparable to wire parasitic effects. Although small transistors are with smaller parasitic capacitance and less power consumption, they will more sensitive to layout mismatch.The function of the TDCs designed and implemented in the thesis is guaranteed for the application but the performance needs to be improved. The layout turns out to be an essential stage for the final characteristics of the circuits. With a more thoughtful design flow and sophisticated consideration for mismatch, the circuits after layout could maintain the performance as schematic level. 40 7 Future work There is plenty of more work to be done to improve the performance of TDC. Due to that the TDC is essential to the aggressive goal of phase noise from all digital PLL, other kinds of architectures of it are worth to try for the required resolution and dynamic range. Since the performance of circuit after layout is not identical with schematic, the size of transistors could be modified for layout oriented. To reduce the parasitic effects, layout should be improved from a better floor plan. Vernier TDC with higher resolution and better linearity could be implemented on layout which can tolerate first order PVT variation if two delay chains are well matched [11]. Although the Vernier TDC and parallel TDC achieve high reso lution, they have very low efficiency when measuring large time intervals, which requires extra hardware and power consumption. To overcome this limitation, a Vernier Ring TDC has been proposed recently.Unlike the conventional Vernier TDC, this novel TDC places the Vernier delay cells in a ring format such that the delay chains can be reused for measuring large time intervals. Digital logic monitors the number of laps the signals propagate along the rings. Arbiters are used to record the location where the lag signal catches up with the lead signal. The reuse of Vernier delay cells in a ring configuration achieves fine resolution and large detectable range simultaneously with small area and low power consumption [11]. This architecture of Vernier Ring TDC combines the Vernier delay lines and GRO topology is worth to implement for wide application. ? ? 41 8 [1] [2] [3] [4] [5] [6] [7]